公开(公告)号：US09214628B2

公开(公告)日：2015-12-15

申请号：US13810245

申请日：2011-11-30

申请人： Atsushi Himeno ,  Haruyuki Sorada ,  Yukio Hayakawa ,  Takumi Mikawa

发明人： Atsushi Himeno ,  Haruyuki Sorada ,  Yukio Hayakawa ,  Takumi Mikawa

IPC分类号： H01L45/00 ,  H01L27/10 ,  H01L27/24 ,  H01L27/105

CPC分类号： H01L45/1253 ,  H01L27/101 ,  H01L27/1052 ,  H01L27/2409 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/16 ,  H01L45/1625 ,  H01L45/1675

摘要： A nonvolatile memory element according to the present invention includes a first metal line; a plug formed on the first metal line and connected to the first metal line; a stacked structure including a first electrode, a second electrode, and a variable resistance layer, the stacked structure being formed on a plug which is connected to the first electrode; a second metal line formed on the stacked structure and directly connected to the second electrode; and a side wall protective layer which covers the side wall of the stacked structure and has an insulating property and an oxygen barrier property, wherein part of a lower surface of the second metal line is located under an upper surface of the stacked structure.

摘要翻译： 根据本发明的非易失性存储元件包括第一金属线; 形成在所述第一金属线上并连接到所述第一金属线的插头; 包括第一电极，第二电极和可变电阻层的堆叠结构，所述堆叠结构形成在连接到所述第一电极的插头上; 形成在所述堆叠结构上并直接连接到所述第二电极的第二金属线; 以及侧壁保护层，其覆盖层叠结构的侧壁，并且具有绝缘性和氧阻隔性，其中第二金属线的下表面的一部分位于堆叠结构的上表面的下方。

公开(公告)号：US08592798B2

公开(公告)日：2013-11-26

申请号：US13641491

申请日：2011-04-21

申请人： Takumi Mikawa ,  Haruyuki Sorada

发明人： Takumi Mikawa ,  Haruyuki Sorada

IPC分类号： H01L29/02

CPC分类号： H01L27/101 ,  G11C13/0007 ,  G11C2213/51 ,  H01L21/76807 ,  H01L21/76849 ,  H01L27/2409 ,  H01L27/2463 ,  H01L27/2481 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/1625 ,  H01L45/1683

摘要： A variable resistance non-volatile storage device includes: a first line which includes a barrier metal layer and a main layer, and fills an inside of a line trench formed in a first interlayer insulating layer; a first electrode covering a top surface of the first line and comprising a precious metal; memory cell holes formed in a second interlayer insulating layer; a variable resistance layer formed in the memory cell holes and connected to the first electrode; and second lines covering the variable resistance layer and the memory cell holes, wherein in an area near the memory cell holes, the main layer is covered with the barrier metal layer and the first electrode in an arbitrary widthwise cross section of the first line.

摘要翻译： 可变电阻非易失性存储装置包括：第一线，其包括阻挡金属层和主层，并填充形成在第一层间绝缘层中的线沟槽的内部; 覆盖第一线的顶表面并包含贵金属的第一电极; 在第二层间绝缘层中形成的存储单元孔; 形成在所述存储单元孔中并连接到所述第一电极的可变电阻层; 以及覆盖可变电阻层和存储单元孔的第二线，其中在存储单元孔附近的区域中，主层被第一线的任意宽度横截面中的阻挡金属层和第一电极覆盖。

公开(公告)号：US20130122651A1

公开(公告)日：2013-05-16

申请号：US13812227

申请日：2011-07-26

申请人： Satoru Fujii ,  Takumi Mikawa ,  Haruyuki Sorada

发明人： Satoru Fujii ,  Takumi Mikawa ,  Haruyuki Sorada

IPC分类号： H01L45/00

CPC分类号： H01L45/1616 ,  H01L27/101 ,  H01L27/2409 ,  H01L27/2418 ,  H01L27/2463 ,  H01L27/2481 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/124 ,  H01L45/145 ,  H01L45/146

摘要： Each of the step of forming a first variable resistance layer (18a) and the step of forming a second variable resistance layer (18b) includes performing a cycle once or plural times, the cycle consisting of a first step of introducing a source gas composed of molecules containing atoms of a transition metal; a second step of removing the source gas after the first step; a third step of introducing a reactive gas to form a transition metal oxide after the second step; and a fourth step of removing the reactive gas after the third step. The step of forming the first variable resistance layer (18a) is performed in a state in which the substrate is kept at a temperature at which a self-decomposition reaction of the source gas does not occur. One or plural of conditions used for forming the second variable resistance layer (18b) is/are made different from the one or plural conditions used for forming the first variable resistance layer (18a), the conditions being the temperature of the substrate, an amount of the introduced source gas and an amount of the introduced reactive gas.

摘要翻译： 形成第一可变电阻层（18a）的步骤和形成第二可变电阻层（18b）的步骤包括执行一次或多次的循环，所述循环包括：引入由 含有过渡金属原子的分子; 在第一步骤之后除去源气体的第二步骤; 在第二步骤之后引入反应气体以形成过渡金属氧化物的第三步骤; 以及在第三步骤之后除去反应气体的第四步骤。 形成第一可变电阻层（18a）的步骤是在基板保持在不发生源气体的自分解反应的温度的状态下进行的。 使用于形成第二可变电阻层（18b）的一个或多个条件与用于形成第一可变电阻层（18a）的一个或多个条件不同，条件是基板的温度， 的引入源气体和一定量的引入的反应气体。

公开(公告)号：US20120199805A1

公开(公告)日：2012-08-09

申请号：US13501228

申请日：2011-08-11

申请人： Haruyuki Sorada ,  Takeki Ninomiya ,  Takumi Mikawa ,  Yukio Hayakawa

发明人： Haruyuki Sorada ,  Takeki Ninomiya ,  Takumi Mikawa ,  Yukio Hayakawa

IPC分类号： H01L47/00 ,  H01L21/02

CPC分类号： H01L27/101 ,  H01L27/2409 ,  H01L27/2463 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/1608 ,  H01L45/1675

摘要： Provided are a nonvolatile memory device which can suppress non-uniformity in initial breakdown voltages among nonvolatile memory elements and prevent reduction of yield, and a manufacturing method thereof. The nonvolatile memory device includes a nonvolatile memory element (108) having a stacked-layer structure in which a resistance variable layer (106) is parallel to a main surface of a substrate (117) and is planarized, and a plug (103) electrically connected to either a first electrode (105) or a second electrode (107), and an area of an end surface of a plug (103) at which the plug (103) and the nonvolatile memory element (108) are connected together, the end surface being parallel to the main surface of the substrate (117), is greater than a cross-sectional area of a cross-section of a first transition metal oxide layer (115) which is an electrically-conductive region, the cross-section being parallel to the main surface of the substrate (117).

摘要翻译： 提供一种能够抑制非易失性存储元件之间的初始击穿电压的不均匀性并且防止产量降低的非易失性存储器件及其制造方法。 非易失性存储器件包括具有堆叠层结构的非易失性存储元件（108），其中电阻变化层（106）平行于衬底（117）的主表面并被平坦化;以及电极（103） 连接到第一电极（105）或第二电极（107），以及插头（103）的端面（103）的与插头（103）和非易失性存储元件（108）连接在一起的区域， 平行于基板（117）的主表面的端面大于作为导电区域的第一过渡金属氧化物层（115）的截面的横截面积，横截面 平行于基板（117）的主表面。

公开(公告)号：US07473967B2

公开(公告)日：2009-01-06

申请号：US10558671

申请日：2004-05-31

申请人： Haruyuki Sorada ,  Takeshi Takagi ,  Akira Asai ,  Yoshihiko Kanzawa ,  Kouji Katayama ,  Junko Iwanaga

发明人： Haruyuki Sorada ,  Takeshi Takagi ,  Akira Asai ,  Yoshihiko Kanzawa ,  Kouji Katayama ,  Junko Iwanaga

IPC分类号： H01L27/088

CPC分类号： H01L29/785 ,  H01L29/66795 ,  H01L29/78687

摘要： A semiconductor device according to this invention includes: a first insulating layer (11); a first body section (13) including an island-shaped semiconductor formed on the first insulating layer; a second body section (14) including an island-shaped semiconductor formed on the first insulating layer; a ridge-shaped connecting section (15) formed on the first insulating layer to interconnect the first body section and the second body section; a channel region (15a) formed by at least a part of the connecting section in lengthwise direction of the connecting section; a gate electrode (18) formed to cover a periphery of the channel region, with a second insulating layer intervening therebetween; a source region formed to extend over the first body section and a portion of the connecting section between the first body section and the channel region; and a drain region formed to extend over the second body section and a portion of the connecting section between the second body section and the channel region, wherein a semiconductor forming the channel region has a lattice strain.

摘要翻译： 根据本发明的半导体器件包括：第一绝缘层（11）; 第一主体部分（13），其包括形成在所述第一绝缘层上的岛状半导体; 包括形成在所述第一绝缘层上的岛状半导体的第二主体部分（14） 形成在第一绝缘层上以互连第一主体部分和第二主体部分的脊形连接部分（15）; 由连接部的长度方向的至少一部分形成的通道区域（15a）; 形成为覆盖沟道区域的周边的栅极电极（18），其间插入有第二绝缘层; 形成为在第一主体部分上延伸的源极区域和在第一主体部分和沟道区域之间的连接部分的一部分; 以及形成为在第二主体部分上延伸的漏极区域和在第二主体部分和沟道区域之间的连接部分的一部分，其中形成沟道区域的半导体具有晶格应变。

公开(公告)号：US20070108514A1

公开(公告)日：2007-05-17

申请号：US10554860

申请日：2004-04-28

申请人： Akira Inoue ,  Takeshi Takagi ,  Haruyuki Sorada

发明人： Akira Inoue ,  Takeshi Takagi ,  Haruyuki Sorada

IPC分类号： H01L29/94

CPC分类号： H01L29/7834 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66621 ,  H01L29/66772 ,  H01L29/78621

摘要： A semiconductor device according to the present invention, which comprises a MISFET, has a semiconductor layer (3) having a recessed portion (101) formed in the surface thereof, the recessed portion (101) having an opening the outer circumference of which is closed, a gate insulating film (13) formed so as to cover at least the inner face of the recessed portion (3), a gate electrode (14) filling the recessed portion (101) such that the gate insulating film (13) is interposed between the gate electrode (14) and the inner face of the recessed portion (101), and a pair of source/drains (102), located on both sides of the gate electrode (14) when viewed in plan and formed to a predetermined depth from the surface of the semiconductor layer (3).

摘要翻译： 根据本发明的包括MISFET的半导体器件具有在其表面形成有凹部（101）的半导体层（3），所述凹部（101）的外周封闭的开口部 形成为至少覆盖所述凹部（3）的内面的栅极绝缘膜（13），填充所述凹部（101）的栅极电极（14），使得所述栅极绝缘膜（13）插入 在栅极电极（14）和凹部（101）的内表面之间，以及一对源极/漏极（102），位于栅极电极（14）的两侧，当从平面观察时形成预定的 从半导体层（3）的表面的深度。

公开(公告)号：US07119417B2

公开(公告)日：2006-10-10

申请号：US10948747

申请日：2004-09-24

申请人： Haruyuki Sorada ,  Takeshi Takagi ,  Akira Inoue ,  Yoshio Kawashima

发明人： Haruyuki Sorada ,  Takeshi Takagi ,  Akira Inoue ,  Yoshio Kawashima

IPC分类号： H01L31/117

CPC分类号： H01L29/66636 ,  H01L21/28202 ,  H01L29/1054 ,  H01L29/518 ,  H01L29/665 ,  H01L29/7833 ,  H01L29/7842

摘要： A semiconductor device of this invention includes: a semiconductor substrate; a gate electrode formed on the semiconductor substrate; a pair of source and drain electrodes respectively formed in regions of the semiconductor substrate situated on opposite sides of the gate electrode in a plan view; and a germanium-containing channel layer situated below the gate electrode to sandwich an gate insulator therebetween and intervening between the pair of source and drain electrodes, wherein a silicide layer forming at least a part of the source and drain electrodes has a lower germanium concentration than the channel layer.

摘要翻译： 本发明的半导体器件包括：半导体衬底; 形成在所述半导体衬底上的栅电极; 在平面图中分别形成在位于栅电极的相对侧的半导体衬底的区域中的一对源极和漏极; 以及位于栅极电极下方的含锗沟道层，以夹持栅极绝缘体，并且介于所述一对源极和漏极之间，其中形成所述源极和漏极的至少一部分的硅化物层的锗浓度低于 通道层。

公开(公告)号：US07087473B2

公开(公告)日：2006-08-08

申请号：US10866093

申请日：2004-06-14

申请人： Haruyuki Sorada ,  Akira Asai ,  Takeshi Takagi ,  Akira Inoue ,  Yoshio Kawashima

发明人： Haruyuki Sorada ,  Akira Asai ,  Takeshi Takagi ,  Akira Inoue ,  Yoshio Kawashima

IPC分类号： H01L29/80

CPC分类号： H01L21/823807

摘要： A semiconductor integrated circuit fabrication method according to this invention includes: a step of forming a pair of first device forming regions and a pair of second device forming regions in a surface layer portion of a semiconductor substrate by surrounding each of the regions by device isolation; a step of forming a first oxide film covering the surface of the semiconductor substrate after the preceding step; a step of removing an intended portion of the first oxide film to expose the pair of second device forming regions; a step of forming a pair of heterojunction structures, by selective epitaxial growth, on the pair of second device forming regions thus exposed; a step of forming a second oxide film covering the surface of the substrate after the preceding step; and a step of forming a pair of gate electrodes above each of the pair of first device forming regions and the pair of second device forming regions, whereby a normal complementary MOS transistor and a heterojunction complementary MOS transistor are eventually formed in the pair of first device forming regions and the pair of second device forming regions, respectively.

摘要翻译： 根据本发明的半导体集成电路制造方法包括：通过器件隔离来围绕每个区域来在半导体衬底的表面层部分中形成一对第一器件形成区域和一对第二器件形成区域的步骤; 在前述步骤之后形成覆盖半导体衬底的表面的第一氧化物膜的步骤; 去除所述第一氧化物膜的预期部分以暴露所述一对第二器件形成区域的步骤; 通过选择性外延生长形成一对异质结结构在由此露出的一对第二器件形成区上的步骤; 在上述步骤之后形成覆盖基板表面的第二氧化膜的步骤; 以及在所述一对第一器件形成区域和所述一对第二器件形成区域中的每一个上形成一对栅电极的步骤，由此在所述一对第一器件形成区域中最终形成正常互补MOS晶体管和异质结互补MOS晶体管 形成区域和一对第二装置形成区域。

公开(公告)号：US20060086988A1

公开(公告)日：2006-04-27

申请号：US11294566

申请日：2005-12-06

申请人： Haruyuki Sorada ,  Akira Asai ,  Takeshi Takagi ,  Akira Inoue ,  Yoshio Kawashima

发明人： Haruyuki Sorada ,  Akira Asai ,  Takeshi Takagi ,  Akira Inoue ,  Yoshio Kawashima

IPC分类号： H01L21/8238 ,  H01L29/94

CPC分类号： H01L21/823807

摘要： A semiconductor integrated circuit fabrication method according to this invention includes: a step of forming a pair of first device forming regions and a pair of second device forming regions in a surface layer portion of a semiconductor substrate by surrounding each of the regions by device isolation; a step of forming a first oxide film covering the surface of the semiconductor substrate after the preceding step; a step of removing an intended portion of the first oxide film to expose the pair of second device forming regions; a step of forming a pair of heterojunction structures, by selective epitaxial growth, on the pair of second device forming regions thus exposed; a step of forming a second oxide film covering the surface of the substrate after the preceding step; and a step of forming a pair of gate electrodes above each of the pair of first device forming regions and the pair of second device forming regions, whereby a normal complementary MOS transistor and a heterojunction complementary MOS transistor are eventually formed in the pair of first device forming regions and the pair of second device forming regions, respectively.

摘要翻译： 根据本发明的半导体集成电路制造方法包括：通过器件隔离来围绕每个区域来在半导体衬底的表面层部分中形成一对第一器件形成区域和一对第二器件形成区域的步骤; 在前述步骤之后形成覆盖半导体衬底的表面的第一氧化物膜的步骤; 去除所述第一氧化物膜的预期部分以暴露所述一对第二器件形成区域的步骤; 通过选择性外延生长形成一对异质结结构在由此露出的一对第二器件形成区上的步骤; 在上述步骤之后形成覆盖基板表面的第二氧化膜的步骤; 以及在所述一对第一器件形成区域和所述一对第二器件形成区域中的每一个上形成一对栅电极的步骤，由此在所述一对第一器件形成区域中最终形成正常互补MOS晶体管和异质结互补MOS晶体管 形成区域和一对第二装置形成区域。

公开(公告)号：US06917075B2

公开(公告)日：2005-07-12

申请号：US10752409

申请日：2004-01-07

申请人： Akira Inoue ,  Akira Asai ,  Teruhito Ohnishi ,  Haruyuki Sorada ,  Yoshihiro Hara ,  Takeshi Takagi

发明人： Akira Inoue ,  Akira Asai ,  Teruhito Ohnishi ,  Haruyuki Sorada ,  Yoshihiro Hara ,  Takeshi Takagi

IPC分类号： H01L21/336 ,  H01L21/768 ,  H01L29/78 ,  H01L29/786 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC分类号： H01L29/66772 ,  H01L21/76895 ,  H01L29/783 ,  H01L29/78615 ,  H01L29/78621

摘要： A semiconductor device and a method of fabricating the same according to this invention are such that: a gate insulator is formed over a predetermined region of a semiconductor substrate; a gate electrode is formed on the gate insulator; source and drain regions respectively formed in portions of the predetermined region that are situated on both sides of the gate electrode in plan view; a body region formed by a region of the predetermined region exclusive of the source and drain regions; and a contact electrically interconnecting the gate electrode and the body region, wherein a portion of the contact which is connected to the gate electrode is formed to intersect the gate electrode in plan view.

摘要翻译： 根据本发明的半导体器件及其制造方法是：在半导体衬底的预定区域上形成栅极绝缘体; 栅电极形成在栅极绝缘体上; 源极和漏极区域分别形成在预定区域的位于栅极电极的两侧的部分中; 由不同于所述源极和漏极区域的所述预定区域的区域形成的体区; 以及使所述栅电极和所述体区域电连接的触点，其中，与所述栅电极连接的所述触点的一部分在平面图中形成为与所述栅电极相交。