公开(公告)号：US20060055452A1

公开(公告)日：2006-03-16

申请号：US11269696

申请日：2005-11-09

申请人： Toru Tanzawa ,  Takeshi Miyaba ,  Shigeru Atsumi

发明人： Toru Tanzawa ,  Takeshi Miyaba ,  Shigeru Atsumi

IPC分类号： G05F1/10

CPC分类号： G11C5/145 ,  G11C5/14 ,  G11C5/147 ,  G11C16/12 ,  G11C16/30

摘要： There are provided a boosted voltage generating circuit and a semiconductor memory device having the boosted voltage generating circuit which includes a booster circuit for outputting high voltage obtained by boosting the power supply voltage, a regulator circuit supplied with the high voltage, for generating voltage whose voltage value is smaller than the value of the high voltage and which is variably set to at least two values based on the high voltage at the operating time, and a equalizer circuit connected to the booster circuit and regulator circuit, for short-circuiting an output node of the booster circuit and an output node of the regulator circuit in response to a first control signal, wherein the operative period of the regulator circuit and the short-circuiting operation period of the equalizer circuit do not overlap each other.

公开(公告)号：US20050162210A1

公开(公告)日：2005-07-28

申请号：US11017923

申请日：2004-12-22

申请人： Toru Tanzawa

发明人： Toru Tanzawa

IPC分类号： H03F3/45 ,  G06G7/14 ,  G06G7/24 ,  H03F3/34 ,  H03G3/30 ,  H04B1/26

CPC分类号： G06G7/14

摘要： A voltage subtracting circuit includes a conversion circuit, a holding circuit, and a differential voltage generator. The conversion circuit converts a first voltage input during a first period into a first current proportional to the first voltage. The conversion circuit further converts a second voltage input during a second period following the first period into a second current proportional to the second voltage. The holding circuit holds the first current during the first period as a third voltage. The holding circuit further outputs the first current during the second period on the basis of the third voltage. The differential voltage generator outputs a differential voltage between the second voltage and the first voltage during the second period on the basis of the second current output by the conversion circuit and the first current output by the holding circuit.

摘要翻译： 减压电路包括转换电路，保持电路和差分电压发生器。 转换电路将第一时段期间的第一电压输入转换成与第一电压成比例的第一电流。 转换电路还在第一周期之后的第二周期期间将第二电压输入转换成与第二电压成比例的第二电流。 保持电路在第一周期期间将第一电流保持为第三电压。 保持电路还基于第三电压在第二时段期间输出第一电流。 差分电压发生器基于由转换电路输出的第二电流和由保持电路输出的第一电流在第二时段期间输出第二电压和第一电压之间的差分电压。

公开(公告)号：US06865125B2

公开(公告)日：2005-03-08

申请号：US10892289

申请日：2004-07-16

申请人： Toru Tanzawa ,  Shigeru Atsumi

发明人： Toru Tanzawa ,  Shigeru Atsumi

IPC分类号： G11C16/06 ,  G11C11/56 ,  G11C16/02 ,  G11C16/28 ,  G11C16/34 ,  G11C29/04 ,  G11C29/42 ,  G11C16/04

CPC分类号： G11C11/5635 ,  G11C7/06 ,  G11C7/1006 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/28 ,  G11C16/344 ,  G11C2211/5641 ,  G11C2211/565

摘要： A non-volatile semiconductor memory comprises a memory cell array having a plurality of non-volatile memory cells, at least one reference cell, a read circuit for reading data by applying a first voltage to one of word lines to compare a current flowing through one of bit lines with a current flowing through the reference cell, an erase circuit for erasing the data by applying a voltage to at least two selected from the word lines, the bit lines, the source lines and a semiconductor region including the memory cells, first and second regulators, and an erase verify circuit for detecting whether the erase has finished by applying an output voltage of the first regulator to word lines of the memory cells to be erased, while applying an output voltage of the second regulator to a word line of the reference cell, thereby comparing a cell current of selected one of the memory cells with a cell current of the reference cell.

摘要翻译： 非易失性半导体存储器包括具有多个非易失性存储器单元的存储单元阵列，至少一个参考单元，用于通过向一个字线施加第一电压来读取数据的读取电路，以比较流过一个的电流 具有流过参考单元的电流的位线;擦除电路，用于通过向包括存储单元的包括字线，位线，源极线和半导体区域中的至少两个电极施加电压来擦除数据，第一 和第二调节器，以及擦除验证电路，用于通过将第一调节器的输出电压施加到要擦除的存储器单元的字线来检测擦除是否已经完成，同时将第二调节器的输出电压施加到 参考单元，从而将所选择的一个存储单元的单元电流与参考单元的单元电流进行比较。

公开(公告)号：US06856548B2

公开(公告)日：2005-02-15

申请号：US10756267

申请日：2004-01-14

申请人： Toru Tanzawa ,  Tadayuki Taura ,  Masao Kuriyama

发明人： Toru Tanzawa ,  Tadayuki Taura ,  Masao Kuriyama

IPC分类号： G11C16/00 ,  G11C16/30 ,  G11C16/34 ,  G11C11/40

CPC分类号： G11C16/107 ,  G11C16/30 ,  G11C16/3409 ,  G11C16/344 ,  G11C16/3445 ,  G11C16/3459 ,  G11C16/3477

摘要： A potential generating circuit generates two types of erase verify threshold values EVT1 and EVT2. These values satisfy the relationship of EVT2=EVT1+(OEVT−EVTL). OEVT is an over-erase verify threshold value. While the erase verify threshold value is set at EVT2, the lower limit of a threshold voltage distribution after data erase is higher than OEVT. EVTL is the lower limit of the threshold voltage distribution after data erase while the erase verify threshold value is set at EVT1 and is lower than OEVT. The erase verify threshold values EVT1 and EVT2 are switched according to an operation mode. During a write/erase test, for example, the erase verify threshold value is set at EVT2. On the other hand, during the normal operation, the erase verify threshold value is set at EVT1.

摘要翻译： 电位产生电路产生两种类型的擦除验证阈值EVT1和EVT2。 这些值满足EVT2 = EVT1 +（OEVT-EVTL）的关系。 OEVT是过擦除验证阈值。 当擦除验证阈值设定为EVT2时，数据擦除后阈值电压分布的下限高于OEVT。 EVTL是数据擦除后的阈值电压分布的下限，擦除验证阈值设定为EVT1，低于OEVT。 根据操作模式切换擦除验证阈值EVT1和EVT2。 在写入/擦除测试期间，例如，擦除验证阈值被设置为EVT2。 另一方面，在正常操作期间，将擦除验证阈值设置为EVT1。

公开(公告)号：US06807097B2

公开(公告)日：2004-10-19

申请号：US10661571

申请日：2003-09-15

申请人： Yoshinori Takano ,  Tadayuki Taura ,  Toru Tanzawa

发明人： Yoshinori Takano ,  Tadayuki Taura ,  Toru Tanzawa

IPC分类号： G11C1604

CPC分类号： G11C16/3472 ,  G11C11/5621 ,  G11C11/5642 ,  G11C16/28 ,  G11C16/3436 ,  G11C16/3481 ,  G11C2211/5621 ,  G11C2211/5634

摘要： A non-volatile semiconductor memory device includes: an array of electrically rewritable nonvolatile data storage memory cells each having a transistor structure with a control gate; reference current source circuit configured to generate a first reference current adaptable for use during an ordinary read operation and a second reference current for use during a verify-read operation for data status verification in one of writing and erasing events; a sense amplifier configured to compare read currents of a selected memory cell as selected during the ordinary read operation and the verify-read operation with the first and second reference currents respectively to thereby perform data detection; and a driver configured to give an identical voltage to the control gate of the selected memory cell presently selected during the ordinary read operation and the verify-read operation.

摘要翻译： 非挥发性半导体存储器件包括：每个具有带控制栅极的晶体管结构的电可重写非易失性数据存储单元的阵列; 参考电流源电路，被配置为生成适于在普通读取操作期间使用的第一参考电流和用于在写入和擦除事件之一中的数据状态验证的验证读取操作期间使用的第二参考电流; 读出放大器，被配置为将普通读取操作期间所选择的所选存储单元的读取电流与验证读取操作分别与第一和第二参考电流进行比较，从而执行数据检测; 以及驱动器，被配置为向在普通读取操作和验证读取操作期间当前选择的所选择的存储器单元的控制栅极提供相同的电压。

公开(公告)号：US06762956B2

公开(公告)日：2004-07-13

申请号：US10241029

申请日：2002-09-11

申请人： Seiichi Mori ,  Toru Tanzawa

发明人： Seiichi Mori ,  Toru Tanzawa

IPC分类号： G11C1604

CPC分类号： G11C16/107 ,  G11C16/14 ,  G11C2216/18

摘要： A semiconductor integrated circuit device includes a memory block. The device performs a programming operation, a pre-programming operation, and an erasing operation. The pre-programming operation by which each of the nonvolatile memory cells in the erased state in the memory block including the nonvolatile memory cells is pre-programmed to an intermediate state between the programmed and erased states.

摘要翻译： 半导体集成电路装置包括存储块。 该装置执行编程操作，预编程操作和擦除操作。 在包括非易失性存储单元的存储器块中被擦除状态的每个非易失性存储单元被预编程到编程和擦除状态之间的中间状态的预编程操作。

公开(公告)号：US06577538B2

公开(公告)日：2003-06-10

申请号：US10197847

申请日：2002-07-19

申请人： Shigeru Atsumi ,  Tadayuki Taura ,  Toru Tanzawa

发明人： Shigeru Atsumi ,  Tadayuki Taura ,  Toru Tanzawa

IPC分类号： G11C1604

CPC分类号： G11C16/16 ,  G11C2216/18

摘要： In a channel-erase EEPROM, there is a parasitic capacitance between node N1 to which a substrate voltage is supplied and node N2 to which the voltage on a word line is supplied. A negative voltage is applied to the word line in erasing the data in a memory cell. A switch circuit SW1 is connected between node N1 and node N2. Between node N1 and the ground, a switch SW4 is connected. A switch SW5 is connected between node N2 and the ground. When the erase operation has been completed, the switch circuit SW1 is first turned on, short-circuiting node N1 and node N2. Thereafter, the switch circuits SW4, SW5 are turned on, grounding node N1 and node N2 separately.

公开(公告)号：US06552936B2

公开(公告)日：2003-04-22

申请号：US10052303

申请日：2002-01-18

申请人： Hitoshi Shiga ,  Yoshinori Takano ,  Toru Tanzawa ,  Shigeru Atsumi

发明人： Hitoshi Shiga ,  Yoshinori Takano ,  Toru Tanzawa ,  Shigeru Atsumi

IPC分类号： G11C1604

CPC分类号： G11C7/1021 ,  G11C8/10

摘要： There is disclosed a semiconductor integrated circuit device comprising a memory cell array, row decoder, sense amplifier, column gate with two or more stages connected in series, column gate driving circuit, data latch, multiplexer, and address control circuit, and the multiplexer sequentially selects data corresponding to a predetermined address from a plurality of data latched by the data latch. The address control circuit reverses a driving signal for driving at least one stage of the column gate with two or more stages connected in series and selects the columns designated by the next selected plurality of addresses, while the multiplexer sequentially selects the data corresponding to the predetermined address.

公开(公告)号：US06487120B2

公开(公告)日：2002-11-26

申请号：US09864181

申请日：2001-05-25

申请人： Toru Tanzawa ,  Takeshi Miyaba ,  Shigeru Atsumi

发明人： Toru Tanzawa ,  Takeshi Miyaba ,  Shigeru Atsumi

IPC分类号： G11C1604

CPC分类号： G11C5/145 ,  G11C5/14 ,  G11C5/147 ,  G11C16/12 ,  G11C16/30

摘要： There are provided a boosted voltage generating circuit and a semiconductor memory device having the boosted voltage generating circuit which includes a booster circuit for outputting high voltage obtained by boosting the power supply voltage, a regulator circuit supplied with the high voltage, for generating voltage whose voltage value is smaller than the value of the high voltage and which is variably set to at least two values based on the high voltage at the operating time, and a equalizer circuit connected to the booster circuit and regulator circuit, for short-circuiting an output node of the booster circuit and an output node of the regulator circuit in response to a first control signal, wherein the operative period of the regulator circuit and the short-circuiting operation period of the equalizer circuit do not overlap each other.

公开(公告)号：US06344996B2

公开(公告)日：2002-02-05

申请号：US09768588

申请日：2001-01-25

申请人： Tomoharu Tanaka ,  Hiroshi Nakamura ,  Toru Tanzawa

发明人： Tomoharu Tanaka ,  Hiroshi Nakamura ,  Toru Tanzawa

IPC分类号： G11C1604

CPC分类号： G11C16/0483 ,  G11C7/1048 ,  G11C11/5621 ,  G11C11/5628 ,  G11C11/5642 ,  G11C11/565 ,  G11C16/26 ,  G11C2211/5642

摘要： A semiconductor memory device comprises memory cells, a bitline connected to the memory cells, a read circuit including a precharge circuit, and a first transistor connected between the bitline and the read circuit, wherein a first voltage is applied to a gate of the first transistor when the precharge circuit precharges the bitline, and a second voltage which is different from the first voltage is applied to the gate of the first transistor when the read circuit senses a change in a voltage of the bitline.

摘要翻译： 半导体存储器件包括存储器单元，连接到存储器单元的位线，包括预充电电路的读取电路和连接在位线和读取电路之间的第一晶体管，其中第一电压施加到第一晶体管的栅极 当预充电电路对位线进行预充电，并且当读取电路感测到位线的电压变化时，与第一电压不同的第二电压被施加到第一晶体管的栅极。