公开(公告)号：US06300656B1

公开(公告)日：2001-10-09

申请号：US08647532

申请日：1996-05-15

申请人： Shuichi Ueno ,  Shigeru Kusunoki ,  Yoshinori Okumura

发明人： Shuichi Ueno ,  Shigeru Kusunoki ,  Yoshinori Okumura

IPC分类号： G11C1134

CPC分类号： H01L29/66492 ,  H01L21/26586 ,  H01L27/115 ,  H01L29/66659 ,  H01L29/7835

摘要： A nonvolatile semiconductor memory device includes an n-type region which is in contact with n+ drain diffusion region at a surface of p-type silicon substrate and covers the periphery thereof. The device also includes a p-type impurity region which is in contact with n-type region and covers the periphery thereof. The n+ drain diffusion region, n-type region and p+ impurity region extend to region located immediately under the floating gate electrode. Thereby, the nonvolatile semiconductor memory device has a structure which can promote injection of high energy electrons along a gate electrode direction.

摘要翻译： 非易失性半导体存储器件包括在p型硅衬底的表面上与n +漏极扩散区域接触并覆盖其周围的n型区域。 该器件还包括与n型区域接触并覆盖其周边的p型​​杂质区域。 n +漏极扩散区域，n型区域和p +杂质区域延伸到位于浮置栅电极正下方的区域。 由此，非易失性半导体存储器件具有能够沿着栅电极方向注入高能电子的结构。

公开(公告)号：US6017781A

公开(公告)日：2000-01-25

申请号：US755734

申请日：1996-11-25

申请人： Satoshi Shimizu ,  Shuichi Ueno ,  Shigenobu Maeda ,  Takashi Ipposhi

发明人： Satoshi Shimizu ,  Shuichi Ueno ,  Shigenobu Maeda ,  Takashi Ipposhi

IPC分类号： H01L21/20 ,  H01L21/265 ,  H01L21/336 ,  H01L27/11 ,  H01L29/78 ,  H01L29/786 ,  H01L21/84

CPC分类号： H01L27/1108 ,  H01L27/1281 ,  H01L27/1285 ,  H01L29/66757 ,  H01L29/78624 ,  H01L29/78675 ,  H01L29/78678 ,  Y10S257/914

摘要： According to a method of manufacturing a thin film transistor (TFT), amorphous silicon is formed by ion-implanting either silicon or nitrogen into a region of polysilicon while a region located at the sidewall of a gate electrode is selectively left using the stepped portion of the gate electrode. Then, a heat treatment is applied to convert the amorphous silicon into polysilicon with the remaining polysilicon as a seed crystal. As a result, polysilicon having crystal grains of great grain size can be formed in uniform. Thus, the electric characteristics of a TFT can be improved with no difference in the electric characteristics between each TFT.

摘要翻译： 根据制造薄膜晶体管（TFT）的方法，通过将硅或氮离子注入到多晶硅的区域中形成非晶硅，而位于栅电极的侧壁的区域选择性地使用步骤部分 栅电极。 然后，进行热处理以将非晶硅转化为多晶硅，剩余的多晶硅作为晶种。 结果，可以均匀地形成具有大晶粒尺寸的晶粒的多晶硅。 因此，可以提高TFT的电特性，并且每个TFT之间的电特性没有差异。

公开(公告)号：US08383427B2

公开(公告)日：2013-02-26

申请号：US13566739

申请日：2012-08-03

申请人： Ryoji Matsuda ,  Shuichi Ueno ,  Haruo Furuta ,  Takashi Takenaga ,  Takeharu Kuroiwa

发明人： Ryoji Matsuda ,  Shuichi Ueno ,  Haruo Furuta ,  Takashi Takenaga ,  Takeharu Kuroiwa

IPC分类号： H01L29/82 ,  G11C11/02

CPC分类号： H01L43/08 ,  H01L27/228 ,  H01L43/12

摘要： A semiconductor device having a MTJ device excellent in operating characteristics and a manufacturing method therefor are provided. The MTJ device is formed of a laminated structure which is obtained by laminating a lower magnetic film, a tunnel insulating film, and an upper magnetic film in this order. The lower and upper magnetic films contain noncrystalline or microcrystalline ferrocobalt boron (CoFeB) as a constituent material. The tunnel insulating film contains aluminum oxide (AlOx) as a constituent material. A CAP layer is formed over the upper magnetic film and a hard mask is formed over the CAP layer. The CAP layer contains a substance of crystalline ruthenium (Ru) as a constituent material and the hard mask contains a substance of crystalline tantalum (Ta) as a constituent material. The film thickness of the hard mask is larger than that of the CAP layer.

摘要翻译： 提供一种具有优异的操作特性的MTJ装置的半导体装置及其制造方法。 MTJ装置由层叠结构形成，其通过依次层叠下磁性膜，隧道绝缘膜和上磁性膜而获得。 下部和上部磁性膜含有非结晶或微晶铁硼（CoFeB）作为构成材料。 隧道绝缘膜包含氧化铝（AlOx）作为构成材料。 在上磁性膜上形成CAP层，在CAP层上形成硬掩模。 CAP层包含结晶钌（Ru）作为构成材料的物质，硬掩模含有结晶钽（Ta）作为构成材料的物质。 硬掩模的膜厚大于CAP层的膜厚。

公开(公告)号：US20110204458A1

公开(公告)日：2011-08-25

申请号：US13099737

申请日：2011-05-03

申请人： Haruo FURUTA ,  Ryoji Matsuda ,  Shuichi Ueno ,  Takeharu Kuroiwa

发明人： Haruo FURUTA ,  Ryoji Matsuda ,  Shuichi Ueno ,  Takeharu Kuroiwa

IPC分类号： H01L29/82 ,  H01L43/12

CPC分类号： H01L43/08 ,  B82Y10/00 ,  H01L27/228 ,  H01L43/12

摘要： The semiconductor device which has a memory cell including the TMR film with which memory accuracy does not deteriorate, and its manufacturing method are obtained. A TMR element (a TMR film, a TMR upper electrode) is selectively formed in the region which corresponds in plan view on a TMR lower electrode in a part of formation area of a digit line. A TMR upper electrode is formed by 30-100 nm thickness of Ta, and functions also as a hard mask at the time of a manufacturing process. The interlayer insulation film formed from LT-SiN on the whole surface of a TMR element and the upper surface of a TMR lower electrode is formed, and the interlayer insulation film which covers the whole surface comprising the side surface of a TMR lower electrode, and includes LT-SiN is formed. The interlayer insulation film which covers the whole surface and includes SiO2 is formed.

摘要翻译： 具有包含记忆精度不劣化的TMR膜的存储单元的半导体装置及其制造方法。 在数字线的形成区域的一部分的TMR下电极的平面图中对应的区域选择性地形成TMR元件（TMR膜，TMR上电极）。 TMR上电极由Ta的30-100nm厚度形成，并且在制造过程中也用作硬掩模。 在TMR元件的整个表面和TMR下电极的整个表面上形成由LT-SiN形成的层间绝缘膜，覆盖包括TMR下电极的侧表面的整个表面的层间绝缘膜和 包括LT-SiN。 形成覆盖整个表面并包含SiO 2的层间绝缘膜。

公开(公告)号：US20090302404A1

公开(公告)日：2009-12-10

申请号：US12463865

申请日：2009-05-11

申请人： Ryoji Matsuda ,  Shuichi Ueno ,  Haruo Furuta ,  Takashi Takenaga ,  Takeharu Kuroiwa

发明人： Ryoji Matsuda ,  Shuichi Ueno ,  Haruo Furuta ,  Takashi Takenaga ,  Takeharu Kuroiwa

IPC分类号： H01L29/82 ,  H01L21/28

CPC分类号： H01L43/08 ,  H01L27/228 ,  H01L43/12

摘要： A semiconductor device having an MTJ device excellent in operating characteristics and a manufacturing method therefor are obtained. The MTJ device is formed of a laminated structure obtained by laminating a lower magnetic film, a tunnel insulating film, and an upper magnetic film in this order. The lower magnetic film and the upper magnetic film contain noncrystalline or microcrystalline ferrocobalt boron (CoFeB) as a constituent material. The tunnel insulating film contains aluminum oxide (AlOx) as a constituent material. A CAP layer is formed over the upper magnetic film of the MTJ device and a hard mask is formed over the CAP layer. The CAP layer contains a simple substance of crystalline ruthenium (Ru) as a constituent material and the hard mask contains a simple substance of crystalline tantalum (Ta) as a constituent material. The hard mask is so formed that the film thickness thereof is larger than the film thickness of the CAP layer.

摘要翻译： 获得具有优异的操作特性的MTJ装置的半导体装置及其制造方法。 MTJ装置由通过依次层叠下磁性膜，隧道绝缘膜和上磁性膜获得的层叠结构形成。 下磁性膜和上磁性膜含有非结晶或微晶铁硼（CoFeB）作为构成材料。 隧道绝缘膜包含氧化铝（AlOx）作为构成材料。 在MTJ装置的上部磁性膜上形成CAP层，在CAP层上形成硬掩模。 CAP层包含结晶钌（Ru）的单一物质作为构成材料，硬掩模含有作为构成材料的结晶钽（Ta）的单一物质。 硬掩模被形成为使得其膜厚度大于CAP层的膜厚度。

公开(公告)号：US07180773B2

公开(公告)日：2007-02-20

申请号：US11253696

申请日：2005-10-20

申请人： Yoshinori Okumura ,  Shuichi Ueno ,  Haruo Furuta

发明人： Yoshinori Okumura ,  Shuichi Ueno ,  Haruo Furuta

IPC分类号： G11C11/14 ,  G11C11/00

CPC分类号： H01L43/08 ,  B82Y10/00 ,  G11C11/15 ,  G11C11/1659 ,  G11C11/1675 ,  H01L27/228

摘要： A width and a thickness of a bit line are represented as W1 and T1, respectively, a thickness of a digit line is represented as T2, and a distance from a center of the digit line in a thickness direction to a center of a free layer of an MTJ element in the thickness direction is represented as L1. A width of the digit line is represented as W2, and a distance from a center of the bit line in the thickness direction to the center of the free layer of the MTJ element in the thickness direction is represented as L2. The distances L1 and L2 and the cross-sectional areas S1 and S2 are set in such a manner that when L1/L2≧1, a relation of (⅓)·(L1/L2)≦S2/S1≦1 is satisfied and when L1/L2≦1, a relation of 1≦S2/S1≦3(L1/L2) is satisfied.

摘要翻译： 位线的宽度和厚度分别表示为W 1和T 1，数字线的厚度表示为T 2，并且从数字线的中心到厚度方向的中心的距离 在厚度方向上的MTJ元件的自由层表示为L 1。 数字线的宽度表示为W 2，并且从厚度方向的位线的中心到厚度方向上的MTJ元件的自由层的中心的距离表示为L 2。 距离L 1和L 2以及横截面积S 1和S 2被设定为当L 1 / L 2> = 1时，关于（1/3）（L 1 / L 2 ）满足<= S 2 / S 1 <= 1，并且当L 1 / L 2 <= 1时，满足1 <= S 2 / S 1 <= 3（L 1 / L 2）的关系。

公开(公告)号：US20060087874A1

公开(公告)日：2006-04-27

申请号：US11253696

申请日：2005-10-20

申请人： Yoshinori Okumura ,  Shuichi Ueno ,  Haruo Furuta

发明人： Yoshinori Okumura ,  Shuichi Ueno ,  Haruo Furuta

IPC分类号： G11C5/06

CPC分类号： H01L43/08 ,  B82Y10/00 ,  G11C11/15 ,  G11C11/1659 ,  G11C11/1675 ,  H01L27/228

摘要： A width and a thickness of a bit line are represented as W1 and T1, respectively, a thickness of a digit line is represented as T2, and a distance from a center of the digit line in a thickness direction to a center of a free layer of an MTJ element in the thickness direction is represented as L1. A width of the digit line is represented as W2, and a distance from a center of the bit line in the thickness direction to the center of the free layer of the MTJ element in the thickness direction is represented as L2. The distances L1 and L2 and the cross-sectional areas S1 and S2 are set in such a manner that when L1/L2≧1, a relation of (⅓)·(L1/L2)≦S2/S1≦1 is satisfied and when L1/L2≦1, a relation of 1≦S2/S1≦3(L1/L2) is satisfied.

摘要翻译： 位线的宽度和厚度分别表示为W 1和T 1，数字线的厚度表示为T 2，并且从数字线的中心到厚度方向的中心的距离 在厚度方向上的MTJ元件的自由层表示为L 1。 数字线的宽度表示为W 2，并且从厚度方向的位线的中心到厚度方向上的MTJ元件的自由层的中心的距离表示为L 2。 距离L 1和L 2以及横截面积S 1和S 2被设定为当L 1 / L 2> = 1时，关于（1/3）（L 1 / L 2 ）满足<= S 2 / S 1 <= 1，并且当L 1 / L 2 <= 1时，满足1 <= S 2 / S 1 <= 3（L 1 / L 2）的关系。

公开(公告)号：US06492690B2

公开(公告)日：2002-12-10

申请号：US09366732

申请日：1999-08-04

申请人： Shuichi Ueno ,  Yoshinori Okumura ,  Shigenobu Maeda ,  Shigeto Maegawa

发明人： Shuichi Ueno ,  Yoshinori Okumura ,  Shigenobu Maeda ,  Shigeto Maegawa

IPC分类号： H01L27088

CPC分类号： H01L27/11526 ,  H01L27/105 ,  H01L27/11546

摘要： According to a semiconductor device and a method of manufacturing the same, a trade-off relationship between threshold values and a diffusion layer leak is eliminated and it is not necessary to form gate oxide films at more than one stages. Since impurity dose are different from each other between gate electrodes (4A to 4C) of N-channel type MOS transistors (T41 to T43), impurity concentration in the gate electrodes (4A to 4C) are different from each other. The impurity concentration in the gate electrodes are progressively lower in the order of higher threshold values which are expected.

摘要翻译： 根据半导体器件及其制造方法，消除了阈值和扩散层泄漏之间的权衡关系，并且不需要在多于一个阶段形成栅极氧化膜。 由于杂质剂量在N沟道型MOS晶体管（T41〜T43）的栅电极（4A〜4C）之间彼此不同，所以栅电极（4A〜4C）中的杂质浓度彼此不同。 栅电极中的杂质浓度按预期的较高阈值的顺序逐渐降低。

公开(公告)号：US06461934B2

公开(公告)日：2002-10-08

申请号：US09862311

申请日：2001-05-23

申请人： Yukio Nishida ,  Shuichi Ueno ,  Masashi Kitazawa

发明人： Yukio Nishida ,  Shuichi Ueno ,  Masashi Kitazawa

IPC分类号： H01L2176

CPC分类号： H01L21/76229

摘要： Trench isolation regions of different depths are formed through a simple manufacturing process, and reliability of a semiconductor device is increased. Trenches (103a, 103b) of different widths are formed on a semiconductor substrate (101) on which an underlying film (104) such as a silicon oxide film and a mask material (105) such as a silicon nitride film are formed. Then, an insulating film such as a silicon oxide film is deposited over the entire surface to such a degree that the narrower trench (103a) is filled up. At this time, the wider trench (103b) has an unfilled space in its central portion. a The surface of the substrate (101) is then vertically etched back until it is exposed in the trench 103b. With insulating films (106a, 106b) in the trenches (103a, 103b) as a mask, the surface of the substrate (101) is anisotropically etched vertically to form a deeper bottom (103c) in the trench (103b). After that, the surface is planarizedby depositing an insulating film in the unfilled space of the trench (103b).

摘要翻译： 通过简单的制造工艺形成不同深度的沟槽隔离区域，并且增加了半导体器件的可靠性。 在半导体衬底（101）上形成不同宽度的沟槽（103a，103b），在其上形成诸如氧化硅膜的底层膜（104）和诸如氮化硅膜的掩模材料（105）。 然后，在整个表面上沉积诸如氧化硅膜的绝缘膜，使得填充较窄的沟槽（103a）的程度。 此时，较宽的沟槽（103b）在其中央部分具有未填充的空间。 a然后将衬底（101）的表面垂直蚀刻回直到其暴露在沟槽103b中。 以沟槽（103a，103b）中的绝缘膜（106a，106b）作为掩模，垂直地各向异性地蚀刻衬底（101）的表面，以在沟槽（103b）中形成更深的底部（103c）。 之后，通过在沟槽（103b）的未填充空间中沉积绝缘膜来平坦化表面。

公开(公告)号：US06300664B1

公开(公告)日：2001-10-09

申请号：US08880508

申请日：1997-06-23

申请人： Takashi Kuroi ,  Shuichi Ueno ,  Hidekazu Oda ,  Satoshi Shimizu

发明人： Takashi Kuroi ,  Shuichi Ueno ,  Hidekazu Oda ,  Satoshi Shimizu

IPC分类号： H01L2976

CPC分类号： H01L29/0847 ,  H01L21/28176 ,  H01L21/28202 ,  H01L21/823857 ,  H01L29/4908 ,  H01L29/4916 ,  H01L29/4933 ,  H01L29/51 ,  H01L29/518 ,  H01L29/665 ,  H01L29/66575 ,  H01L29/6659 ,  H01L29/66765 ,  H01L29/7833 ,  H01L29/78618

摘要： Obtained are a semiconductor device which can prevent diffusion of an impurity contained in a gate electrode and a method of fabricating the same. In this semiconductor device, a gate oxide film and a P+-type gate electrode which are formed on a P-type silicon substrate are doped with nitrogen.

摘要翻译： 获得的是能够防止栅电极中所含杂质扩散的半导体器件及其制造方法。 在该半导体器件中，形成在P型硅衬底上的栅极氧化膜和P +型栅极掺杂有氮。