公开(公告)号：US10283206B2

公开(公告)日：2019-05-07

申请号：US15792590

申请日：2017-10-24

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  Anh Ly ,  Thuan Vu ,  Hung Quoc Nguyen ,  Vipin Tiwari

IPC: G11C16/28 ,  G11C16/06 ,  H01L27/11519 ,  G11C16/24 ,  G11C16/00 ,  G11C7/06 ,  G11C7/12 ,  G11C16/26

Abstract: Improved flash memory sensing circuits are disclosed. In one embodiment, a sensing circuit comprises a memory data read block, a memory reference block, a differential amplifier, and a precharge circuit. The precharge circuit compensates for parasitic capacitance between a bit line coupled to a selected memory cell and adjacent bit lines.

公开(公告)号：US20190080754A1

公开(公告)日：2019-03-14

申请号：US16119416

申请日：2018-08-31

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  Anh Ly ,  Thuan Vu ,  Stanley Hong ,  Feng Zhou ,  Xian Liu ,  Nhan Do

IPC: G11C13/00 ,  H01L27/24 ,  H01L45/00

Abstract: Numerous embodiments of methods for writing to a resistive random access memory (RRAM) cell are disclosed. In one embodiment, the system verifies if a current through the RRAM cell exceeds a threshold value, and if it does not, the system executes a concurrent write-while-verify operation. In another embodiment, the system verifies if current through the RRAM cell has reached a target value, and if it has not, the system executes a write operation and then verifies the write operation using a current comparison.

公开(公告)号：US20190066805A1

公开(公告)日：2019-02-28

申请号：US15687092

申请日：2017-08-25

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  Anh Ly ,  Thuan Vu ,  Stanley Hong

IPC: G11C16/28 ,  G11C16/34

Abstract: Numerous embodiments for an improved sense amplifier circuit for reading data in a flash memory cell are disclosed. The embodiments each compare current or voltage measurements from a data block with a reference block to determine the value stored in the selected memory cell in the data block. The use of one or more localized boost circuits allow the embodiments to utilize lower operating voltages than prior art sense amplifier circuits, resulting in reduced power consumption.

公开(公告)号：US10186322B2

公开(公告)日：2019-01-22

申请号：US15361473

申请日：2016-11-27

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  Anh Ly ,  Thuan Vu ,  Hung Quoc Nguyen

IPC: G11C16/30 ,  G11C16/14 ,  G11C16/04 ,  G11C16/08 ,  G11C5/14 ,  G11C8/08 ,  G11C16/10 ,  G11C16/16 ,  G11C16/26 ,  H01L27/11521

Abstract: A non-volatile memory device comprises a semiconductor substrate of a first conductivity type. An array of non-volatile memory cells is located in the semiconductor substrate and arranged in a plurality of rows and columns. Each memory cell comprises a first region on a surface of the semiconductor substrate of a second conductivity type, and a second region on the surface of the semiconductor substrate of the second conductivity type. A channel region is between the first region and the second region. A word line overlies a first portion of the channel region and is insulated therefrom, and adjacent to the first region and having little or no overlap with the first region. A floating gate overlies a second portion of the channel region, is adjacent to the first portion, and is insulated therefrom and is adjacent to the second region. A coupling gate overlies the floating gate. A bit line is connected to the first region. During the operations of program, read, or erase, a negative voltage can be applied to the word lines and/or coupling gates of the selected or unselected memory cells.

公开(公告)号：US20180233203A1

公开(公告)日：2018-08-16

申请号：US15952155

申请日：2018-04-12

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  Anh Ly ,  Thuan Vu ,  Hung Quoc Nguyen

IPC: G11C16/14 ,  G11C16/28 ,  G11C8/08 ,  G11C16/08 ,  G11C16/26 ,  H01L27/112 ,  G11C16/10 ,  G11C7/06

CPC classification number: G11C16/14 ,  G11C7/065 ,  G11C8/08 ,  G11C16/08 ,  G11C16/10 ,  G11C16/26 ,  G11C16/28 ,  G11C2216/04 ,  H01L27/112 ,  H01L27/11582 ,  H01L28/00

Abstract: The present invention relates to a flash memory system comprising one or more sense amplifiers for reading data stored in flash memory cells. The sense amplifiers utilize fully depleted silicon-on-insulator transistors to minimize leakage. The fully depleted silicon-on-insulator transistors comprise one or more fully depleted silicon-on-insulator NMOS transistors and/or one or more fully depleted silicon-on-insulator PMOS transistors.

公开(公告)号：US09972395B2

公开(公告)日：2018-05-15

申请号：US14875533

申请日：2015-10-05

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  Anh Ly ,  Thuan Vu ,  Hung Quoc Nguyen

IPC: G11C16/04 ,  G11C16/14 ,  G11C16/08 ,  G11C16/26 ,  G11C7/06 ,  G11C8/08 ,  G11C16/10 ,  G11C16/28 ,  H01L27/112

CPC classification number: G11C16/14 ,  G11C7/065 ,  G11C8/08 ,  G11C16/08 ,  G11C16/10 ,  G11C16/26 ,  G11C16/28 ,  G11C2216/04 ,  H01L27/112 ,  H01L27/11582 ,  H01L28/00

Abstract: The present invention relates to a flash memory system wherein one or more circuit blocks utilize fully depleted silicon-on-insulator transistor design to minimize leakage.

公开(公告)号：US09953719B2

公开(公告)日：2018-04-24

申请号：US15158460

申请日：2016-05-18

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  Anh Ly ,  Thuan Vu

IPC: G11C11/34 ,  G11C16/34 ,  G11C16/16 ,  G11C16/08 ,  G11C16/28

CPC classification number: G11C16/3431 ,  G11C16/0425 ,  G11C16/08 ,  G11C16/10 ,  G11C16/16 ,  G11C16/28

Abstract: The present invention relates to a flash memory cell with only four terminals and decoder circuitry for operating an array of such flash memory cells. The invention allows for fewer terminals for each flash memory cell compared to the prior art, which results in a simplification of the decoder circuitry and overall die space required per flash memory cells. The invention also provides for the use of high voltages on one or more of the four terminals to allow for read, erase, and programming operations despite the lower number of terminals compared to prior art flash memory cells.

公开(公告)号：US20180053560A1

公开(公告)日：2018-02-22

申请号：US15479235

申请日：2017-04-04

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  Anh Ly ,  Thuan Vu ,  Vipin Tiwari ,  Nhan Do

IPC: G11C16/34 ,  G11C16/14 ,  G11C16/24 ,  G11C16/26 ,  G11C16/08

CPC classification number: G11C16/08 ,  G11C16/0425 ,  G11C16/10 ,  G11C16/14 ,  G11C16/24 ,  G11C16/26 ,  G11C16/28 ,  G11C16/32 ,  G11C16/3418 ,  G11C16/3427 ,  G11C2216/04 ,  G11C2216/22

Abstract: In one embodiment of the present invention, one row is selected and two columns are selected for a read or programming operation, such that twice as many flash memory cells can be read from or programmed in a single operation compared to the prior art. In another embodiment of the present invention, two rows in different sectors are selected and one column is selected for a read operation, such that twice as many flash memory cells can be read in a single operation compared to the prior art.

公开(公告)号：US20180053553A1

公开(公告)日：2018-02-22

申请号：US15238681

申请日：2016-08-16

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  Anh Ly ,  Thuan Vu ,  Vipin Tiwari ,  Nhan Do

IPC: G11C16/08 ,  G11C16/14 ,  G11C16/24 ,  G11C16/34 ,  G11C16/26

CPC classification number: G11C16/08 ,  G11C16/0425 ,  G11C16/10 ,  G11C16/14 ,  G11C16/24 ,  G11C16/26 ,  G11C16/28 ,  G11C16/32 ,  G11C16/3418 ,  G11C16/3427 ,  G11C2216/04 ,  G11C2216/22

Abstract: In one embodiment of the present invention, one row is selected and two columns are selected for a read or programming operation, such that twice as many flash memory cells can be read from or programmed in a single operation compared to the prior art. In another embodiment of the present invention, two rows in different sectors are selected and one column is selected for a read operation, such that twice as many flash memory cells can be read in a single operation compared to the prior art.

公开(公告)号：US20160351267A1

公开(公告)日：2016-12-01

申请号：US14726124

申请日：2015-05-29

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  Anh Ly ,  Thuan Vu ,  Hung Quoc Nguyen ,  Viet Tan Nguyen

IPC: G11C16/30 ,  G11C16/10 ,  G11C16/28 ,  G11C16/08

CPC classification number: G11C16/30 ,  G11C5/14 ,  G11C8/10 ,  G11C16/08 ,  G11C16/10 ,  G11C16/28 ,  G11C16/32 ,  G11C29/14 ,  G11C2207/2227

Abstract: The present invention relates to a circuit and method for low power operation in a flash memory system. In disclosed embodiments of a selection-decoding circuit path, pull-up and pull-down circuits are used to save values at certain output nodes during a power save or shut down modes, which allows the main power source to be shut down while still maintaining the values.

Abstract translation: 本发明涉及一种用于闪存系统中的低功率操作的电路和方法。 在选择解码电路路径的所公开的实施例中，上拉和下拉电路用于在节电或关断模式期间在某些输出节点处保存值，这允许主电源在仍然保持时被关闭 价值。