公开(公告)号：US12238932B2

公开(公告)日：2025-02-25

申请号：US18298342

申请日：2023-04-10

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Rainer Yen-Chieh Huang ,  Hai-Ching Chen ,  Yu-Ming Lin ,  Chung-Te Lin

IPC: H10B51/20 ,  H01L21/28 ,  H01L23/528 ,  H01L29/51 ,  H01L29/78 ,  H10B41/23 ,  H10B51/30

Abstract: A ferroelectric memory device, a manufacturing method of the ferroelectric memory device and a semiconductor chip are provided. The ferroelectric memory device includes a gate electrode, a ferroelectric layer, a channel layer, first and second blocking layers, and source/drain electrodes. The ferroelectric layer is disposed at a side of the gate electrode. The channel layer is capacitively coupled to the gate electrode through the ferroelectric layer. The first and second blocking layers are disposed between the ferroelectric layer and the channel layer. The second blocking layer is disposed between the first blocking layer and the channel layer. The first and second blocking layers comprise a same material, and the second blocking layer is further incorporated with nitrogen. The source/drain electrodes are disposed at opposite sides of the gate electrode, and electrically connected to the channel layer.

公开(公告)号：US20240379858A1

公开(公告)日：2024-11-14

申请号：US18779506

申请日：2024-07-22

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Wu-Wei Tsai ,  Hai-Ching Chen

IPC: H01L29/786 ,  H01L29/66

Abstract: In some embodiments, the present disclosure relates to a device. The device includes an active layer arranged over a substrate. A gate electrode is arranged on a first side of the active layer and spaced apart from the active layer by a gate dielectric layer. A passivation structure is arranged on the active layer. A source contact extends through the passivation structure to contact the active layer and a drain contact extends through the passivation structure to contact the active layer. An upper portion of the passivation structure includes silicon carbide.

公开(公告)号：US20240373641A1

公开(公告)日：2024-11-07

申请号：US18772364

申请日：2024-07-15

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Rainer Yen-Chieh Huang ,  Hai-Ching Chen ,  Chung-Te Lin

IPC: H10B51/30 ,  H01L21/28 ,  H01L23/522 ,  H01L29/51 ,  H01L29/66 ,  H01L29/78 ,  H01L29/786 ,  H10B51/00

Abstract: In some embodiments, the present disclosure relates to an integrated chip that includes a gate electrode over a substrate, and a gate dielectric layer arranged over the gate electrode. The gate dielectric layer includes a ferroelectric material. An active structure is arranged over the gate dielectric layer and includes a semiconductor material. A source contact and a drain contact are arranged over the active structure. A capping structure is arranged between the source and drain contacts and over the active structure. The capping structure includes a first metal material.

公开(公告)号：US12027601B2

公开(公告)日：2024-07-02

申请号：US17815253

申请日：2022-07-27

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： Yen-Chieh Huang ,  Hai-Ching Chen ,  Yu-Ming Lin ,  Chung-Te Lin

IPC: H01L29/51 ,  H01L21/28 ,  H01L29/78

CPC classification number: H01L29/516 ,  H01L29/40111 ,  H01L29/517 ,  H01L29/7831 ,  H01L29/78391

Abstract: A method for forming a semiconductor structure is provided. The method includes following operations. A layer stack is formed over the substrate. The formation of the layer stack includes the following sub-operations: a blocking layer is formed over the substrate, a lower conductive layer is formed over the blocking layer, a first seed layer is formed over the lower conductive layer, a ferroelectric layer is formed over the first seed layer, and an upper conductive layer is formed over the ferroelectric layer. The layer stack is patterned to form a gate stack over the substrate. A spacer layer is formed over sidewalls of the gate stack. A pattered interlayer dielectric layer is formed over the substrate and the gate stack. A source region and a drain region are formed in the substrate through the patterned interlayer dielectric layer.

公开(公告)号：US12002750B2

公开(公告)日：2024-06-04

申请号：US17571029

申请日：2022-01-07

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Hsin-Yen Huang ,  Shao-Kuan Lee ,  Cheng-Chin Lee ,  Hai-Ching Chen ,  Shau-Lin Shue

IPC: H01L29/40 ,  H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L23/5226 ,  H01L21/76816 ,  H01L21/76877 ,  H01L23/5283 ,  H01L29/66795 ,  H01L29/785

Abstract: An interconnect structure is provided. The interconnect structure includes a first metal line and a second metal line surrounded by a first dielectric layer, a dielectric block over a portion of the first dielectric layer between the first metal line and the second metal line, and a second dielectric layer over the dielectric block, the first metal line and the second metal line. A bottom surface of the second dielectric layer is lower than a top surface of the dielectric block. The interconnect structure also includes a first via surrounded by the second dielectric layer and electrically connected to the first metal line.

公开(公告)号：US20240145571A1

公开(公告)日：2024-05-02

申请号：US18150259

申请日：2023-01-05

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Po-Ting Lin ,  Yu-Ming Hsiang ,  Wei-Chih Wen ,  Yin-Hao Wu ,  Wu-Wei Tsai ,  Hai-Ching Chen ,  Yu-Ming Lin ,  Chung-Te Lin

IPC: H01L29/51 ,  H01L21/02 ,  H01L29/66 ,  H01L29/78 ,  H10B51/30

CPC classification number: H01L29/516 ,  H01L21/02178 ,  H01L21/02194 ,  H01L21/0228 ,  H01L29/66969 ,  H01L29/78391 ,  H10B51/30

Abstract: In some embodiments, the present disclosure relates to an integrated circuit (IC) in which a memory structure comprises an inhibition layer inserted between two ferroelectric layers to create a tetragonal-phase dominant ferroelectric structure. In some embodiments, the ferroelectric structure includes a first ferroelectric layer, a second ferroelectric layer overlying the first ferroelectric layer, and a first inhibition layer disposed between the first and second ferroelectric layers and bordering the second ferroelectric layer. The first inhibition layer is a different material than the first and second ferroelectric layers.

公开(公告)号：US20240055517A1

公开(公告)日：2024-02-15

申请号：US17886472

申请日：2022-08-12

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Kuo-Chang Chiang ,  Yu-Chuan Shih ,  Chun-Chieh Lu ,  Po-Ting Lin ,  Hai-Ching Chen ,  Sai-Hooi Yeong ,  Yu-Ming Lin ,  Chung-Te Lin

IPC: H01L29/78 ,  H01L27/1159 ,  H01L29/51 ,  H01L29/66

CPC classification number: H01L29/78391 ,  H01L27/1159 ,  H01L29/516 ,  H01L29/6684

Abstract: Provided are a ferroelectric memory device and a method of forming the same. The ferroelectric memory device includes: a gate electrode; a ferroelectric layer, disposed on the gate electrode; a channel layer, disposed on the ferroelectric layer; a pair of source/drain (S/D) electrodes, disposed on the channel layer; a first insertion layer, disposed between the gate electrode and the ferroelectric layer; and a second insertion layer, disposed between the ferroelectric layer and the channel layer, wherein the second insertion layer has a thickness less than a thickness of the first insertion layer.

公开(公告)号：US20240023342A1

公开(公告)日：2024-01-18

申请号：US18363049

申请日：2023-08-01

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Yen-Chieh Huang ,  Hai-Ching Chen ,  Chung-Te Lin

IPC: H10B51/30 ,  H10B51/00

CPC classification number: H10B51/30 ,  H10B51/00 ,  H01L28/75 ,  H01L2924/1441

Abstract: An integrated chip including a semiconductor layer over a substrate. A pair of source/drains are arranged along the semiconductor layer. A first metal layer is over the substrate. A second metal layer is over the first metal layer. A ferroelectric layer is over the second metal layer. The first metal layer has a first crystal orientation and the second metal layer has a second crystal orientation different from the first crystal orientation.

公开(公告)号：US20240006538A1

公开(公告)日：2024-01-04

申请号：US17857021

申请日：2022-07-03

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Wu-Wei Tsai ,  Po-Ting Lin ,  Kai-Wen Cheng ,  Sai-Hooi Yeong ,  Han-Ting Tsai ,  Ya-Ling Lee ,  Hai-Ching Chen ,  Chung-Te Lin ,  Yu-Ming Lin

IPC: H01L29/786 ,  H01L29/66 ,  H01L27/1159

CPC classification number: H01L29/7869 ,  H01L29/66742 ,  H01L27/1159

Abstract: A method of forming a semiconductor device is provided. A gate electrode is formed within an insulating layer that overlies a substrate. A gate dielectric layer is formed over the gate electrode. A first oxide semiconductor layer is formed over the gate dielectric layer. A dielectric layer is formed over the first oxide semiconductor layer. The dielectric layer and the first oxide semiconductor layer are patterned, so as to form first and second openings that expose portions of the gate dielectric layer. An interfacial layer is conformally formed on sidewalls and bottoms of the first and second openings. A second oxide semiconductor layer is formed over the interfacial layer in the first and second openings. A metal layer is formed over the second oxide semiconductor layer in the first and second openings.

公开(公告)号：US20230268438A1

公开(公告)日：2023-08-24

申请号：US18308791

申请日：2023-04-28

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Yen-Chieh Huang ,  Po-Ting Lin ,  Hai-Ching Chen ,  Sai-Hooi Yeong ,  Yu-Ming Lin ,  Chung-Te Lin

IPC: H01L29/78 ,  H01L29/786 ,  H01L29/49 ,  H10B51/20

CPC classification number: H01L29/78391 ,  H01L29/78693 ,  H01L29/78642 ,  H01L29/4908 ,  H10B51/20

Abstract: A semiconductor device is described. The semiconductor device includes a substrate and a metal layer disposed on the substrate. A seed layer is formed on the metal layer. A ferroelectric gate layer is formed on the seed layer. A channel layer is formed over the ferroelectric gate layer. The seed layer is arranged to increase the orthorhombic phase fraction of the ferroelectric gate layer.