公开(公告)号：US20150214096A1

公开(公告)日：2015-07-30

申请号：US14682823

申请日：2015-04-09

Applicant: Texas Instruments Incorporated

Inventor： Binghua HU ,  Sameer PENDHARKAR ,  Guru MATHUR ,  Takehito TAMURA

IPC: H01L21/762 ,  H01L21/3205 ,  H01L21/02 ,  H01L21/265 ,  H01L21/283

CPC classification number: H01L21/76224 ,  H01L21/02109 ,  H01L21/265 ,  H01L21/283 ,  H01L21/32055 ,  H01L21/76232 ,  H01L29/0619

Abstract: The width of a heavily-doped sinker is substantially reduced by forming the heavily-doped sinker to lie in between a number of closely-spaced trench isolation structures, which have been formed in a semiconductor material. During drive-in, the closely-spaced trench isolation structures significantly limit the lateral diffusion.

Abstract translation: 通过形成重掺杂沉降片位于已形成于半导体材料中的多个紧密间隔的沟槽隔离结构之间，大大减小了重掺杂沉降片的宽度。 在进入期间，紧密间隔的沟槽隔离结构显着限制了横向扩散。

公开(公告)号：US20150171212A1

公开(公告)日：2015-06-18

申请号：US14567196

申请日：2014-12-11

Applicant: Texas Instruments Incorporated

Inventor： Philip Leland HOWER ,  Sameer PENDHARKAR ,  Marie DENISON

IPC: H01L29/78 ,  H01L29/08 ,  H01L29/10 ,  H01L27/088 ,  H01L21/266 ,  H01L21/324 ,  H01L21/225 ,  H01L29/66 ,  H01L29/06

CPC classification number: H01L29/66681 ,  H01L21/2253 ,  H01L21/266 ,  H01L27/088 ,  H01L29/0619 ,  H01L29/0623 ,  H01L29/063 ,  H01L29/0634 ,  H01L29/0642 ,  H01L29/0646 ,  H01L29/0692 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/0886 ,  H01L29/1095 ,  H01L29/66659 ,  H01L29/7816 ,  H01L29/7835

Abstract: An integrated circuit and method having an extended drain MOS transistor with a buried drift region, a drain diffused link, a channel diffused link, and an isolation link which electrically isolated the source, where the isolation diffused link is formed by implanting through segmented areas to dilute the doping to less than two-thirds the doping in the drain diffused link.

Abstract translation: 一种集成电路和方法，其具有具有埋入漂移区域的扩展漏极MOS晶体管，漏极扩散链路，沟道扩散链路和电隔离源极的隔离链路，其中通过分割区域注入形成隔离扩散链路 将掺杂稀释到漏极扩散链路中的掺杂的三分之二以下。

公开(公告)号：US20150097231A1

公开(公告)日：2015-04-09

申请号：US14044926

申请日：2013-10-03

Applicant: Texas Instruments Incorporated

Inventor： Guru MATHUR ,  Marie DENISON ,  Sameer PENDHARKAR

IPC: H01L29/78 ,  H01L29/10 ,  H01L29/08 ,  H01L29/66

CPC classification number: H01L29/063 ,  H01L21/266 ,  H01L21/76232 ,  H01L21/823418 ,  H01L21/823456 ,  H01L27/088 ,  H01L29/0653 ,  H01L29/0878 ,  H01L29/0882 ,  H01L29/1095 ,  H01L29/407 ,  H01L29/42368 ,  H01L29/4238 ,  H01L29/66734 ,  H01L29/7809 ,  H01L29/7811 ,  H01L29/7813

Abstract: A semiconductor device having a vertical drain extended MOS transistor may be formed by forming deep trench structures to define at least one vertical drift region bounded on at least two opposite sides by the deep trench structures. The deep trench structures include dielectric liners. The deep trench structures are spaced so as to form RESURF regions for the drift region. Vertical gates are formed in vertically oriented gate trenches in the dielectric liners of the deep trench structures, abutting the vertical drift regions. A body implant mask for implanting dopants for the transistor body is also used as an etch mask for forming the vertically oriented gate trenches in the dielectric liners.

公开(公告)号：US20140329370A1

公开(公告)日：2014-11-06

申请号：US13886652

申请日：2013-05-03

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Naveen TIPIRNENI ,  Sameer PENDHARKAR ,  Rick L. WISE

IPC: H01L21/02

CPC classification number: H01L21/187 ,  H01L21/76254 ,  H01L21/8258

Abstract: An integrated silicon and III-N semiconductor device may be formed by growing III-N semiconductor material on a first silicon substrate having a first orientation. A second silicon substrate with a second, different, orientation has a release layer between a silicon device film and a carrier wafer. The silicon device film is attached to the III-N semiconductor material while the silicon device film is connected to the carrier wafer through the release layer. The carrier wafer is subsequently removed from the silicon device film. A first plurality of components is formed in and/or on the silicon device film. A second plurality of components is formed in and/or on III-N semiconductor material in the exposed region. In an alternate process, a dielectric interlayer may be disposed between the silicon device film and the III-N semiconductor material in the integrated silicon and III-N semiconductor device.

Abstract translation: 可以通过在具有第一取向的第一硅衬底上生长III-N半导体材料来形成集成的硅和III-N半导体器件。 具有第二不同取向的第二硅衬底在硅器件膜和载体晶片之间具有释放层。 硅器件膜附着到III-N半导体材料上，而硅器件膜通过释放层连接到载体晶片。 随后从硅器件膜移除载体晶片。 在硅器件膜上和/或上形成第一多个部件。 在暴露区域中的III-N半导体材料中和/或上形成第二组分。 在替代方法中，可以在集成硅和III-N半导体器件中的硅器件膜和III-N半导体材料之间设置电介质中间层。

公开(公告)号：US20140327011A1

公开(公告)日：2014-11-06

申请号：US13886429

申请日：2013-05-03

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Sameer PENDHARKAR ,  Naveen TIPIRNENI ,  Jungwoo JOH

IPC: H01L29/20

CPC classification number: H01L29/2003 ,  H01L27/085 ,  H01L29/41725 ,  H01L29/42316 ,  H01L29/66431 ,  H01L29/66462 ,  H01L29/778 ,  H01L29/7787

Abstract: A semiconductor device containing a GaN FET has an isolating gate structure outside the channel area which is operable to block current in the two-dimensional electron gas between two regions of the semiconductor device. The isolating gate structure is formed concurrently with the gate of the GaN FET, and has a same structure as the gate.

Abstract translation: 包含GaN FET的半导体器件具有在沟道区域外部的隔离栅极结构，其可操作以阻挡半导体器件的两个区域之间的二维电子气体中的电流。 隔离栅极结构与GaN FET的栅极同时形成，并且具有与栅极相同的结构。

公开(公告)号：US20140252367A1

公开(公告)日：2014-09-11

申请号：US13789949

申请日：2013-03-08

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Sameer PENDHARKAR ,  Naveen TIPIRNENI

IPC: H01L27/088 ,  H01L21/8236

CPC classification number: H03K17/6872 ,  H01L21/823418 ,  H01L21/823456 ,  H01L21/823462 ,  H01L21/823475 ,  H01L21/8236 ,  H01L21/8252 ,  H01L21/8258 ,  H01L27/0605 ,  H01L27/0883 ,  H01L27/092 ,  H01L27/0922 ,  H01L29/16 ,  H01L29/2003 ,  H01L29/66446 ,  H01L29/7833 ,  H02M5/2573 ,  H03F3/193 ,  H03F3/195 ,  H03K17/6871 ,  H03K17/6877 ,  H03K2017/6875

Abstract: A semiconductor device includes a depletion mode GaN FET and an integrated driver/cascode IC. The integrated driver/cascode IC includes an enhancement mode cascoded NMOS transistor which is connected in series to a source node of the GaN FET. The integrated driver/cascode IC further includes a driver circuit which conditions a gate input signal and provides a suitable digital waveform to a gate node of the cascoded NMOS transistor. The cascoded NMOS transistor and the driver circuit are formed on a same silicon substrate.

Abstract translation: 半导体器件包括耗尽型GaN FET和集成驱动器/共源共栅IC。 集成驱动器/共源共极集成电路包括与GaN FET的源极节点串联连接的增强型共模NMOS晶体管。 集成驱动器/共源共极IC还包括驱动电路，其调节栅极输入信号并向级联的NMOS晶体管的栅极节点提供合适的数字波形。 级联的NMOS晶体管和驱动电路形成在同一个硅衬底上。

公开(公告)号：US20140042452A1

公开(公告)日：2014-02-13

申请号：US13886410

申请日：2013-05-03

Applicant: Texas Instruments Incorporated

Inventor： Sameer PENDHARKAR ,  Naveen TIPIRNENI

IPC: H01L29/20 ,  H01L29/66

CPC classification number: H01L29/2003 ,  H01L21/8252 ,  H01L21/8258 ,  H01L27/0605 ,  H01L29/1066 ,  H01L29/42316 ,  H01L29/4236 ,  H01L29/66477 ,  H01L29/7786

Abstract: A semiconductor device includes an enhancement mode GaN FET with a depletion mode GaN FET electrically coupled in series between a gate node of the enhancement mode GaN FET and a gate terminal of the semiconductor device. A gate node of the depletion mode GaN FET is electrically coupled to a source node of the enhancement mode GaN FET. A source node of said enhancement mode GaN FET is electrically coupled to a source terminal of the semiconductor device, a drain node of the enhancement mode GaN FET is electrically coupled to a drain terminal of said semiconductor device, and a drain node of the depletion mode GaN FET is electrically coupled to a gate terminal of the semiconductor device.

Abstract translation: 半导体器件包括在增强型GaN FET的栅极节点和半导体器件的栅极端子之间串联电耦合的耗尽型GaN FET的增强型GaN FET。 耗尽型GaN FET的栅极节点电耦合到增强型GaNFET的源极节点。 所述增强型GaN FET的源节点电耦合到半导体器件的源极端子，增强型GaNFET的漏极节点电耦合到所述半导体器件的漏极端子，并且耗尽模式的漏极节点 GaN FET电耦合到半导体器件的栅极端子。

公开(公告)号：US20230369482A1

公开(公告)日：2023-11-16

申请号：US18357431

申请日：2023-07-24

Applicant: Texas Instruments Incorporated

Inventor： Dong Seup LEE ,  Jungwoo JOH ,  Pinghai HAO ,  Sameer PENDHARKAR

IPC: H01L29/778 ,  H01L29/417 ,  H01L29/08 ,  H01L29/06 ,  H01L21/265 ,  H01L29/20 ,  H01L29/66 ,  H01L29/423

CPC classification number: H01L29/7786 ,  H01L29/41775 ,  H01L29/0843 ,  H01L29/0603 ,  H01L21/2654 ,  H01L29/2003 ,  H01L21/26546 ,  H01L29/66462 ,  H01L29/66431 ,  H01L29/0607 ,  H01L29/42316 ,  H01L29/0891

Abstract: In some examples, a transistor comprises a gallium nitride (GaN) layer; a GaN-based alloy layer having a top side and disposed on the GaN layer, wherein source, drain, and gate contact structures are supported by the GaN layer; and a first doped region positioned in a drain access region and extending from the top side into the GaN layer.

公开(公告)号：US20210159329A1

公开(公告)日：2021-05-27

申请号：US17165697

申请日：2021-02-02

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Dong Seup LEE ,  Jungwoo JOH ,  Pinghai HAO ,  Sameer PENDHARKAR

IPC: H01L29/778 ,  H01L29/20 ,  H01L29/06 ,  H01L29/08 ,  H01L21/265 ,  H01L29/66 ,  H01L29/417

Abstract: In some examples, a transistor comprises a gallium nitride (GaN) layer; a GaN-based alloy layer having a top side and disposed on the GaN layer, wherein source, drain, and gate contact structures are supported by the GaN layer; and a first doped region positioned in a drain access region and extending from the top side into the GaN layer.

公开(公告)号：US20200381552A1

公开(公告)日：2020-12-03

申请号：US16995133

申请日：2020-08-17

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Marie DENISON ,  Sameer PENDHARKAR ,  Guru MATHUR

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/10 ,  H01L29/08 ,  H01L21/8234 ,  H01L29/40 ,  H01L29/06 ,  H01L29/423 ,  H01L21/225 ,  H01L21/283 ,  H01L21/324 ,  H01L29/51

Abstract: A semiconductor device having a vertical drain extended MOS transistor may be formed by forming deep trench structures to define vertical drift regions of the transistor, so that each vertical drift region is bounded on at least two opposite sides by the deep trench structures. The deep trench structures are spaced so as to form RESURF regions for the drift region. Trench gates are formed in trenches in the substrate over the vertical drift regions. The body regions are located in the substrate over the vertical drift regions.