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    INTEGRATED CIRCUIT
    35.
    发明申请
    INTEGRATED CIRCUIT 有权
    集成电路

    公开(公告)号：US20140355330A1

    公开(公告)日：2014-12-04

    申请号：US14369974

    申请日：2012-12-04

    Applicant: TOHOKU UNIVERSITY

    Inventor： Tetsuo Endoh ,  Takashi Ohsawa ,  Hiroki Koike ,  Takahiro Hanyu ,  Hideo Ohno

    IPC: G11C13/00

    CPC classification number: G11C13/0038 ,  G11C11/161 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1675 ,  G11C11/1693 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0069 ,  G11C14/00 ,  G11C14/0081 ,  G11C15/046 ,  G11C19/02 ,  G11C29/50012 ,  H03K3/356139 ,  H03K3/59 ,  H03K19/18

    Abstract: An integrated circuit that does not involve increase in power consumption or decrease in switching probability that occur when a latch circuit using STT-MTJ device, etc. of the prior art is operated at high speed is provided. The integrated circuit 1 includes: a memory element 1B where write occurs when a specified period τ has elapsed after a write signal is input; and a basic circuit element 1A, which is an elementary device constituting a circuit and has a data retaining function, and characterized in that an operation frequency f1 in a first operation mode in the process of information processing of the basic circuit element 1A satisfies the following relation: τ>λ1/f1(0

    Abstract translation: 提供了当使用现有技术的STT-MTJ装置等的锁存电路以高速运行时，不涉及增加功耗或降低切换概率的集成电路。 集成电路1包括：存储元件1B，其中在写入信号被输入之后经过了指定的周期τ时发生写入; 以及作为构成电路并具有数据保持功能的基本装置的基本电路元件1A，其特征在于，在基本电路元件1A的信息处理的处理中的第一动作模式中的动作频率f1满足以下 关系：τ>λ1/ f1（0 <λ1＆nlE; 1）。

    MAGNETIC STACKED FILM AND MAGNETORESISTIVE EFFECT ELEMENT
    36.
    发明申请
    MAGNETIC STACKED FILM AND MAGNETORESISTIVE EFFECT ELEMENT 有权

    公开(公告)号：US20250031581A1

    公开(公告)日：2025-01-23

    申请号：US18569910

    申请日：2022-06-15

    Applicant: TOHOKU UNIVERSITY

    Inventor： Yoshiaki Saito ,  Tetsuo Endoh ,  Shoji Ikeda

    IPC: H10N50/10 ,  G11C11/16 ,  H10B61/00 ,  H10N50/85 ,  H10N52/85

    Abstract: There is provided a stacked film that allows flowing a write current and achieves a high-density and/or high-speed memory and a magnetoresistive effect element using the stacked film. A magnetic stacked film 10 is formed of a three-layered structure that includes a first ferromagnetic layer 12, an antiferromagnetic coupling layer 10a provided on the first ferromagnetic layer 12, and a second ferromagnetic layer 16 provided on the antiferromagnetic coupling layer 10a. The antiferromagnetic coupling layer 10a includes a first non-magnetic layer 13, an interlayer coupling layer 14, and a second non-magnetic layer 15. The interlayer coupling layer 14 is selected from a metal or an alloy including at least any one of Ir, Ru, and Rh. The first non-magnetic layer 13 and the second non-magnetic layer 15 are selected from a metal or an alloy including Pt.

    Nonvolatile logic circuit
    37.
    发明授权
    Nonvolatile logic circuit 有权

    公开(公告)号：US11790966B2

    公开(公告)日：2023-10-17

    申请号：US17417917

    申请日：2019-11-28

    Applicant: TOHOKU UNIVERSITY

    Inventor： Masanori Natsui ,  Takahiro Hanyu ,  Tetsuo Endoh

    IPC: G11C11/16 ,  H03K19/18 ,  H10B61/00 ,  H10N50/80 ,  H03K19/20

    CPC classification number: G11C11/161 ,  H03K19/18 ,  H10B61/00 ,  H10N50/80 ,  H03K19/20

    Abstract: A nonvolatile logic circuit includes: a memory unit having a pair of resistive memory elements; a computation unit connected to the memory unit and configured to perform an operation based on an input signal and a logic value corresponding to a resistance state of the pair of resistive memory elements; a determination circuit configured to determine whether the resistance state of the pair of resistive memory elements is a complementary state or a non-complementary state; and an output circuit connected to the computation unit and the determination circuit, and configured to output a signal corresponding to an operation result by the computation unit or a signal corresponding to a determination result by the determination circuit.

    Magnetoresistance effect element and magnetic memory
    38.
    发明授权
    Magnetoresistance effect element and magnetic memory 有权

    公开(公告)号：US11765981B1

    公开(公告)日：2023-09-19

    申请号：US17264655

    申请日：2019-06-21

    Applicant: TOHOKU UNIVERSITY

    Inventor： Sadahiko Miura ,  Hiroaki Honjo ,  Hideo Sato ,  Shoji Ikeda ,  Tetsuo Endoh

    IPC: G11C11/00 ,  H10N50/10 ,  G11C11/16

    CPC classification number: H10N50/10 ,  G11C11/161

    Abstract: A magnetoresistance effect element with a small element size can be provided which achieves both an increase in a thermal stability factor Δ and a reduction in a writing current IC0 and which improves a performance index Δ/IC0(μA−1) obtained by dividing the thermal stability factor Δ by the writing current IC0. The magnetoresistance effect element includes a first reference layer (B1), a first junction layer (11), a first magnetic layer (21), a first non-magnetic coupling layer (31), a second magnetic layer (22), and a second junction layer (12), and a film thickness of the first non-magnetic coupling layer (31) is 0.1 nm or more and 0.3 nm or less.

    Lookup table circuit comprising a programmable logic device having a selection circuit connected to a memory cell array and separated from a path of a read circuit
    39.
    发明授权
    Lookup table circuit comprising a programmable logic device having a selection circuit connected to a memory cell array and separated from a path of a read circuit 有权

    公开(公告)号：US11610615B2

    公开(公告)日：2023-03-21

    申请号：US17274099

    申请日：2018-09-07

    Applicant: TOHOKU UNIVERSITY

    Inventor： Takahiro Hanyu ,  Daisuke Suzuki ,  Tetsuo Endoh

    IPC: G11C11/16

    Abstract: A lookup table circuit constituting a programmable logic device includes: a memory cell array including a plurality of memory cells, each having a resistive memory element; a selection circuit connected to the memory cell array and configured to output, to the memory cell array, a single cell-select signal or two or more cell-select signals for selecting a single memory cell or two or more memory cells among the plurality of memory cells, based on input of a plurality of logic signals; and a read circuit connected to the memory cell array and configured to read data from the single memory cell or the two or more memory cells selected by the single cell-select signal or the two or more cell-select signals, among the plurality of memory cells. The selection circuit is separated from a path along which the read circuit is configured to read data from the memory cell array.

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