公开(公告)号：US20200152773A1

公开(公告)日：2020-05-14

申请号：US16746547

申请日：2020-01-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Cheng CHING ,  Chih-Hao Wang ,  Shi Ning Ju

IPC: H01L29/66 ,  H01L21/8239 ,  H01L29/78 ,  H01L21/3105 ,  H01L21/8238 ,  H01L29/417

Abstract: A method of forming first and second fin field effect transistors (finFETs) on a substrate includes forming first and second fin structures of the first and second finFETs, respectively, on the substrate. The first and second fin structures have respective first and second vertical dimensions that are about equal to each other. The method further includes modifying the first fin structure such that the first vertical dimension of the first fin structure is smaller than the second vertical dimension of the second fin structure and depositing a dielectric layer on the modified first fin structure and the second fin structure. The method further includes forming a polysilicon structure on the dielectric layer and selectively forming a spacer on a sidewall of the polysilicon structure.

公开(公告)号：US20200083107A1

公开(公告)日：2020-03-12

申请号：US16681621

申请日：2019-11-12

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Kuo-Cheng CHING ,  Shi-Ning JU ,  Kuan-Lun CHENG ,  Chih-Hao WANG

IPC: H01L21/8234 ,  H01L27/088

Abstract: Methods for manufacturing semiconductor structures are provided. The method includes alternately stacking first epitaxy layers and second epitaxy layers to form a semiconductor stack and forming a first mask structure and a second mask structure over the semiconductor stack. The method further includes forming spacers on sidewalls of the second mask and patterning the semiconductor stack to form a first fin structure covered by the first mask structure and a second fin structure covered by the second mask structure and the spacers. The method further includes removing the first epitaxy layers of the first fin structure to form first nanostructures and removing the first epitaxy layers of the second fin structure to form second nanostructures. In addition, the second nanostructures are wider than the first nanostructures.

公开(公告)号：US20200035558A1

公开(公告)日：2020-01-30

申请号：US16422559

申请日：2019-05-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Cheng CHING ,  Lin-Yu HUANG ,  Huan-Chieh SU ,  Sheng-Tsung WANG ,  Zhi-Chang LIN ,  Jia-Chuan YOU ,  Chia-Hao CHANG ,  Tien-Lu LIN ,  Yu-Ming LIN ,  Chih-Hao WANG

IPC: H01L21/768 ,  H01L21/28 ,  H01L29/40 ,  H01L29/78

Abstract: A method of forming a semiconductor device includes providing a device having a gate stack including a metal gate layer. The device further includes a spacer layer disposed on a sidewall of the gate stack and a source/drain feature adjacent to the gate stack. The method further includes performing a first etch-back process to the metal gate layer to form an etched-back metal gate layer. In some embodiments, the method includes depositing a metal layer over the etched-back metal gate layer. In some cases, a semiconductor layer is formed over both the metal layer and the spacer layer to provide a T-shaped helmet layer over the gate stack and the spacer layer.

公开(公告)号：US20190237464A1

公开(公告)日：2019-08-01

申请号：US16380818

申请日：2019-04-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Cheng CHING ,  Kuan-Lun CHENG ,  Chih-Hao WANG ,  Sai-Hooi YEONG ,  Tzer-Min SHEN ,  Chi-Hsing HSU

IPC: H01L27/088 ,  H01L29/66 ,  H01L29/51 ,  H01L29/78 ,  H01L21/265 ,  H01L21/28 ,  H01L21/308 ,  H01L21/311 ,  H01L21/8234

CPC classification number: H01L27/0886 ,  H01L21/26506 ,  H01L21/3086 ,  H01L21/31144 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823468 ,  H01L29/40111 ,  H01L29/511 ,  H01L29/516 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785

Abstract: Devices and methods of forming a FET including a substrate having a first fin and a second fin extending therefrom. A high-k gate dielectric layer and a ferroelectric insulator layer are deposited over the first fin and the second fin. In some embodiments, a dummy gate layer is deposited over the ferroelectric insulator layer over the first fin and the second fin to form a first gate stack over the first fin and a second gate stack over the second fin. The dummy gate layer of the first gate stack is then removed (while maintaining the ferroelectric insulator layer) to form a first trench. And the dummy gate layer and the ferroelectric insulator layer of the second gate stack are removed to form a second trench. At least one metal gate layer is formed in the first trench and the second trench.

公开(公告)号：US20190172926A1

公开(公告)日：2019-06-06

申请号：US16204849

申请日：2018-11-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Cheng CHING ,  Chih-Hao WANG ,  Ching-Wei TSAI ,  Kuan-Lun CHENG

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/45 ,  H01L21/3065 ,  H01L21/02

Abstract: A method of forming a fin field effect transistors (finFET) on a substrate includes forming a fin structure on the substrate, forming a protective layer on the fin structure, and forming a polysilicon structure on the protective layer. The method further includes modifying the polysilicon structure such that a first horizontal dimension of a first portion of the modified polysilicon structure is smaller than a second horizontal dimension of a second portion of the modified polysilicon structure. The method further includes replacing the modified polysilicon structure with a gate structure having a first horizontal dimension of a first portion of the gate structure that is smaller than a second horizontal dimension of a second portion of the gate structure.

公开(公告)号：US20190148490A1

公开(公告)日：2019-05-16

申请号：US16226088

申请日：2018-12-19

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Ka-Hing FUNG ,  Kuo-Cheng CHING ,  Ying-Keung LEUNG

IPC: H01L29/06 ,  H01L29/786 ,  H01L29/78 ,  H01L29/66 ,  H01L21/02 ,  H01L21/306 ,  H01L29/423

Abstract: A semiconductor device includes first channel layers disposed over a substrate, a first source/drain region disposed over the substrate, a gate dielectric layer disposed on and wrapping each of the first channel layers, a gate electrode layer disposed on the gate dielectric layer and wrapping each of the first channel layers, and a liner semiconductor layer disposed between the first channel layers and the first source/drain region.

公开(公告)号：US20190067451A1

公开(公告)日：2019-02-28

申请号：US16023640

申请日：2018-06-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Cheng CHING ,  Chih-Hao WANG ,  Shi Ning JU

IPC: H01L29/66 ,  H01L21/8239 ,  H01L29/78 ,  H01L21/3105 ,  H01L21/8238 ,  H01L21/02

Abstract: A method of forming first and second fin field effect transistors (finFETs) on a substrate includes forming first and second fin structures of the first and second finFETs, respectively, on the substrate. The first and second fin structures have respective first and second vertical dimensions that are about equal to each other. The method further includes modifying the first fin structure such that the first vertical dimension of the first fin structure is smaller than the second vertical dimension of the second fin structure and depositing a dielectric layer on the modified first fin structure and the second fin structure. The method further includes forming a polysilicon structure on the dielectric layer and selectively forming a spacer on a sidewall of the polysilicon structure.

公开(公告)号：US20190067120A1

公开(公告)日：2019-02-28

申请号：US15724411

申请日：2017-10-04

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Cheng CHING ,  Chih-Hao Wang ,  Shi Ning Ju ,  Kuan-Lun Cheng ,  Kuan-Ting Pan

IPC: H01L21/8234 ,  H01L29/66 ,  H01L27/088 ,  H01L27/092 ,  H01L29/78 ,  H01L21/8238

Abstract: The present disclosure relates to a semiconductor device and a manufacturing method, and more particularly to a semiconductor device having self-aligned isolation structures. The present disclosure provides self-aligned isolation fins that can be formed by depositing dielectric material in openings formed in a spacing layer or by replacing portions of fins with dielectric material. The self-aligned isolation fins can be separated from each other by a critical dimension of the utilized photolithography process. The separation between self-aligned isolation fins or between the self-aligned isolation fins and active fins can be approximately equal to or larger than the separations of the active fins.

公开(公告)号：US20160204260A1

公开(公告)日：2016-07-14

申请号：US14592591

申请日：2015-01-08

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD

Inventor： Kuo-Cheng CHING

IPC: H01L29/78 ,  H01L29/10 ,  H01L29/423 ,  H01L29/66 ,  H01L21/02 ,  H01L27/088 ,  H01L29/06

CPC classification number: H01L29/7851 ,  H01L21/02236 ,  H01L29/0673 ,  H01L29/165 ,  H01L29/42376 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/7848

Abstract: Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a semiconductor substrate and a fin channel structure over the semiconductor substrate. The semiconductor device structure also includes a gate stack covering a portion of the fin channel structure. The semiconductor device structure further includes a source/drain structure adjacent to the fin channel structure and a doped region between the semiconductor substrate and the fin channel structure. In addition, the semiconductor device structure includes a blocking layer between the fin channel structure and the doped region.

Abstract translation: 提供半导体器件结构的结构和形成方法。 半导体器件结构包括在半导体衬底上的半导体衬底和鳍状沟道结构。 半导体器件结构还包括覆盖鳍状沟道结构的一部分的栅极堆叠。 半导体器件结构还包括与鳍式沟道结构相邻的源极/漏极结构以及半导体衬底和鳍状沟道结构之间的掺杂区域。 此外，半导体器件结构包括在鳍状沟道结构和掺杂区域之间的阻挡层。

公开(公告)号：US20250142955A1

公开(公告)日：2025-05-01

申请号：US19010734

申请日：2025-01-06

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Cheng CHING ,  Ching-Wei TSAI ,  Kuan-Lun CHENG ,  Chih-Hao WANG

IPC: H10D84/85 ,  H10D30/01 ,  H10D30/62

Abstract: A method for fabricating a semiconductor device includes providing a fin in a first region of a substrate. The fin includes a plurality of a first type of epitaxial layers and a plurality of a second type of epitaxial layers. A portion of a layer of the second type of epitaxial layers in a channel region of the first fin is removed to form a first gap between a first layer of the first type of epitaxial layers and a second layer of the first type of epitaxial layers. A first portion of a first gate structure is formed within the first gap and extending from a first surface of the first layer of the first type of epitaxial layers to a second surface of the second layer of the first type of epitaxial layers. A first source/drain feature is formed abutting the first portion of the first gate structure.