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    METHODS FOR FORMING INTERCONNECT STRUCTURES
    32.
    发明申请
    METHODS FOR FORMING INTERCONNECT STRUCTURES 有权
    形成互连结构的方法

    公开(公告)号：US20130049226A1

    公开(公告)日：2013-02-28

    申请号：US13666050

    申请日：2012-11-01

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Chung-Shi LIU ,  Chen-Hua YU

    IPC: H01L23/522

    CPC classification number: H01L21/7682 ,  H01L21/76825 ,  H01L21/76826 ,  H01L21/76831 ,  H01L21/76832 ,  H01L21/76849 ,  H01L21/76867

    Abstract: A method for forming a semiconductor structure includes forming a sacrificial layer over a substrate. A first dielectric layer is formed over the sacrificial layer. A plurality of conductive structures are formed within the sacrificial layer and the first dielectric layer. The sacrificial layer is treated through the first dielectric layer, at least partially removing the sacrificial layer and forming at least one air gap between two of the conductive structures. A surface of the first dielectric layer is treated, forming a second dielectric layer over the first dielectric layer, after the formation of the air gap. A third dielectric layer is formed over the second dielectric layer. At least one opening is formed within the third dielectric layer such that the second dielectric layer substantially protects the first dielectric layer from damage by the step of forming the opening.

    Abstract translation: 一种用于形成半导体结构的方法包括在衬底上形成牺牲层。 在牺牲层上形成第一介电层。 在牺牲层和第一介电层内形成多个导电结构。 牺牲层通过第一介电层进行处理，至少部分去除牺牲层并在两个导电结构之间形成至少一个气隙。 处理第一电介质层的表面，在形成气隙之后在第一介电层上形成第二电介质层。 在第二电介质层上形成第三电介质层。 至少一个开口形成在第三电介质层内，使得第二电介质层基本上保护第一电介质层不受形成开口的步骤的损害。

    Cross-Wafer RDLs in Constructed Wafers
    34.
    发明申请
    Cross-Wafer RDLs in Constructed Wafers 有权

    公开(公告)号：US20220254656A1

    公开(公告)日：2022-08-11

    申请号：US17660501

    申请日：2022-04-25

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

    Inventor： Chen-Hua YU ,  Tin-Hao KUO

    IPC: H01L21/56 ,  H01L21/768 ,  H01L23/00 ,  H01L25/18 ,  H01L23/522 ,  H01L23/538 ,  H01L23/31

    Abstract: A method includes placing a plurality of package components over a carrier, encapsulating the plurality of package components in an encapsulant, forming a light-sensitive dielectric layer over the plurality of package components and the encapsulant, exposing the light-sensitive dielectric layer using a lithography mask, and developing the light-sensitive dielectric layer to form a plurality of openings. Conductive features of the plurality of package components are exposed through the plurality of openings. The method further includes forming redistribution lines extending into the openings. One of the redistribution lines has a length greater than about 26 mm. The redistribution lines, the plurality of package components, the encapsulant in combination form a reconstructed wafer.

    REDISTRIBUTION LAYER STRUCTURES FOR INTEGRATED CIRCUIT PACKAGE
    35.
    发明申请
    REDISTRIBUTION LAYER STRUCTURES FOR INTEGRATED CIRCUIT PACKAGE 有权

    公开(公告)号：US20210351130A1

    公开(公告)日：2021-11-11

    申请号：US17366575

    申请日：2021-07-02

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd

    Inventor： Jie CHEN ,  Ying-Ju CHEN ,  Hsien-Wei CHEN ,  Der-Chyang YEH ,  Chen-Hua YU

    IPC: H01L23/528 ,  H01L23/00 ,  H01L25/10 ,  H01L23/522 ,  H01L25/00

    Abstract: A method of forming an integrated circuit (IC) package with improved performance and reliability is disclosed. The method includes forming a singulated IC die, coupling the singulated IC die to a carrier substrate, and forming a routing structure. The singulated IC die has a conductive via and the conductive via has a peripheral edge. The routing structure has a conductive structure coupled to the conductive via. The routing structure further includes a cap region overlapping an area of the conductive via, a routing region having a first width from a top-down view, and an intermediate region having a second width from the top-down view along the peripheral edge of the conductive via. The intermediate region is arranged to couple the cap region to the routing region and the second width is greater than the first width.

    SEMICONDUCTOR DEVICE STRUCTURE
    36.
    发明申请
    SEMICONDUCTOR DEVICE STRUCTURE 审中-公开

    公开(公告)号：US20200075412A1

    公开(公告)日：2020-03-05

    申请号：US16676778

    申请日：2019-11-07

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

    Inventor： Chen-Hua YU ,  Chuei-Tang WANG

    IPC: H01L21/768 ,  H01L23/498 ,  H01L21/683 ,  H01L21/56 ,  H01L25/065 ,  H01L21/48 ,  H01L23/552 ,  H01L23/31 ,  H01L23/48 ,  H01L23/00 ,  H01L49/02

    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate. The semiconductor device structure includes a first conductive structure passing through the substrate. The semiconductor device structure includes a conductive shielding structure passing through the substrate and surrounding the first insulating layer. The semiconductor device structure includes a second insulating layer passing through the substrate and surrounding the conductive shielding structure. The semiconductor device structure includes a second conductive structure passing through the substrate. The semiconductor device structure includes a third insulating layer passing through the substrate and surrounding the second conductive structure. The semiconductor device structure includes a conductive layer passing through the first insulating layer.

    STACKED STRUCTURES AND METHODS OF FORMING STACKED STRUCTURES
    39.
    发明申请
    STACKED STRUCTURES AND METHODS OF FORMING STACKED STRUCTURES 审中-公开
    堆叠结构和形成堆叠结构的方法

    公开(公告)号：US20140220741A1

    公开(公告)日：2014-08-07

    申请号：US14251678

    申请日：2014-04-14

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Weng-Jin WU ,  Wen-Chih CHIOU ,  Chen-Hua YU

    IPC: H01L21/78

    CPC classification number: H01L21/78 ,  H01L23/585 ,  H01L25/0657 ,  H01L2225/06513 ,  H01L2225/06527 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A stacked structure includes a first die bonded over a second die. The first die has a first die area defined over a first surface. At least one first protective structure is formed over the first surface, around the first die area. At least one side of the first protective structure has at least one first extrusion part extending across a first scribe line around the protective structure. The second die has a second die area defined over a second surface. At least one second protective structure is formed over the second surface, around the second die area. At least one side of the second protective structure has at least one second extrusion part extending across a second scribe line around the protective structure, wherein the first extrusion part is connected with the second extrusion part.

    Abstract translation: 层叠结构包括在第二管芯上结合的第一管芯。 第一管芯具有限定在第一表面上的第一管芯区域。 在第一表面，围绕第一模具区域形成至少一个第一保护结构。 第一保护结构的至少一侧具有至少一个在保护结构周围延伸穿过第一划线的第一挤压部分。 第二模具具有限定在第二表面上的第二模具区域。 在第二表面上围绕第二管芯区域形成至少一个第二保护结构。 第二保护结构的至少一侧具有至少一个在保护结构周围延伸穿过第二划线的第二挤压部分，其中第一挤压部分与第二挤压部分连接。

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