公开(公告)号：US09659981B2

公开(公告)日：2017-05-23

申请号：US13743979

申请日：2013-01-17

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Shyh-Fann Ting ,  Chih-Yu Lai ,  Cheng-Ta Wu ,  Yeur-Luen Tu ,  Ching-Chun Wang

IPC: H01L27/146

CPC classification number: H01L27/146 ,  H01L27/1463 ,  H01L27/1464 ,  H01L27/14683

Abstract: A semiconductor image sensor device having a negatively-charged layer includes a semiconductor substrate having a p-type region, a plurality of radiation-sensing regions in the p-type region proximate a front side of the semiconductor substrate, and a negatively-charged layer adjoining the p-type region proximate the plurality of radiation-sensing regions. The negatively-charged layer may be an oxygen-rich silicon oxide, a high-k metal oxide, or a silicon nitride formed as a liner in a shallow trench isolation feature, a sidewall spacer or an offset spacer of a transistor gate, a salicide-block layer, a buffer layer under a salicide-block layer, a backside surface layer, or a combination of these.

公开(公告)号：US09425343B2

公开(公告)日：2016-08-23

申请号：US14016996

申请日：2013-09-03

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Yu Lai ,  Cheng-Ta Wu ,  Yeur-Luen Tu ,  Chia-Shiung Tsai ,  Jhy-Jyi Sze ,  Shyh-Fann Ting ,  Ching-Chun Wang

IPC: H01L27/146 ,  H01L31/18

CPC classification number: H01L31/18 ,  H01L27/14614 ,  H01L27/14643

Abstract: Embodiments of mechanisms for forming an image sensor device are provided. The image sensor device includes a semiconductor substrate and one photodetector formed in the semiconductor substrate. The image sensor device also includes one gate stack formed over the semiconductor substrate. The gate stack includes multiple polysilicon layers.

Abstract translation: 提供了用于形成图像传感器装置的机构的实施例。 图像传感器装置包括形成在半导体衬底中的半导体衬底和一个光电检测器。 图像传感器装置还包括形成在半导体衬底上的一个栅叠层。 栅堆叠包括多个多晶硅层。

公开(公告)号：US20150243763A1

公开(公告)日：2015-08-27

申请号：US14187850

申请日：2014-02-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Hung Cheng ,  Cheng-Ta Wu ,  Yeur-Luen Tu ,  Chia-Shiung Tsai ,  Ru-Liang Lee ,  Tung-I Lin ,  Wei-Li Chen

IPC: H01L29/66

CPC classification number: H01L29/42364 ,  H01L21/02532 ,  H01L21/02579 ,  H01L21/0262 ,  H01L21/02636 ,  H01L27/14614 ,  H01L27/14638 ,  H01L29/0649 ,  H01L29/0688 ,  H01L29/1037 ,  H01L29/105 ,  H01L29/1054 ,  H01L29/16 ,  H01L29/165 ,  H01L29/4236 ,  H01L29/66636 ,  H01L29/66651 ,  H01L29/66666 ,  H01L29/66795 ,  H01L29/785

Abstract: The present disclosure relates to a method of generating a transistor device having an epitaxial layer disposed over a recessed active region. The epitaxial layer improves transistor device performance. In some embodiments, the method is performed by providing a semiconductor substrate. An epitaxial growth is performed to form an epitaxial layer onto the semiconductor substrate. An electrically insulating layer is then formed onto the epitaxial layer, and a gate structure is formed onto the electrically insulating layer. By forming the epitaxial layer over the semiconductor substrate the surface roughness of the semiconductor substrate is improved, thereby improving transistor device performance.

Abstract translation: 本公开涉及一种生成具有设置在凹入的有源区上的外延层的晶体管器件的方法。 外延层改善晶体管器件的性能。 在一些实施例中，通过提供半导体衬底来执行该方法。 进行外延生长以在半导体衬底上形成外延层。 然后在外延层上形成电绝缘层，并且在电绝缘层上形成栅极结构。 通过在半导体衬底上形成外延层，改善了半导体衬底的表面粗糙度，从而提高了晶体管器件的性能。

公开(公告)号：US11710656B2

公开(公告)日：2023-07-25

申请号：US16812533

申请日：2020-03-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Ta Wu ,  Kuan-Liang Liu

IPC: H01L21/762 ,  H01L27/12 ,  H01L21/84

CPC classification number: H01L21/76245 ,  H01L21/84 ,  H01L27/1203

Abstract: The present disclosure, in some embodiments, relates to a method of forming a semiconductor structure. The method includes forming a plurality of bulk micro defects within a handle substrate. Sizes of the plurality of bulk micro defects are increased to form a plurality of bulk macro defects (BMDs) within the handle substrate. Some of the plurality of BMDs are removed from within a first denuded region and a second denuded region arranged along opposing surfaces of the handle substrate. An insulating layer is formed onto the handle substrate. A device layer comprising a semiconductor material is formed onto the insulating layer. The first denuded region and the second denuded region vertically surround a central region of the handle substrate that has a higher concentration of the plurality of BMDs than both the first denuded region and the second denuded region.

公开(公告)号：US20220102397A1

公开(公告)日：2022-03-31

申请号：US17036202

申请日：2020-09-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Ta Wu ,  Kuo-Hwa Tzeng ,  Yeur-Luen Tu

IPC: H01L27/146

Abstract: The present disclosure relates to an image sensor having a photodiode surrounded by a back-side deep trench isolation (BDTI) structure, and an associated method of formation. In some embodiments, a plurality of pixel regions is disposed within an image sensing die and respectively comprises a photodiode configured to convert radiation into an electrical signal. The photodiode comprises a photodiode doping column with a first doping type surrounded by a photodiode doping layer with a second doping type that is different than the first doping type. A BDTI structure is disposed between adjacent pixel regions and extending from the back-side of the image sensor die to a position within the photodiode doping layer. The BDTI structure comprises a doped liner with the second doping type and a dielectric fill layer. The doped liner lines a sidewall surface of the dielectric fill layer.

公开(公告)号：US11232974B2

公开(公告)日：2022-01-25

申请号：US16546798

申请日：2019-08-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Hung Cheng ,  Pu-Fang Chen ,  Cheng-Ta Wu ,  Po-Jung Chiang ,  Ru-Liang Lee ,  Victor Y. Lu ,  Yen-Hsiu Chen ,  Yeur-Luen Tu ,  Yu-Lung Yeh ,  Shi-Chieh Lin

IPC: H01L21/762 ,  H01L21/02

Abstract: Various embodiments of the present application are directed to a method for forming a semiconductor-on-insulator (SOI) device with an impurity competing layer to absorb potential contamination metal particles during an annealing process, and the SOI structure thereof. In some embodiments, an impurity competing layer is formed on the dummy substrate. An insulation layer is formed over a support substrate. A front side of the dummy wafer is bonded to the insulation layer. An annealing process is performed and the impurity competing layer absorbs metal from an upper portion of the dummy substrate. Then, a majority portion of the dummy substrate is removed including the impurity competing layer, leaving a device layer of the dummy substrate on the insulation layer.

公开(公告)号：US11158534B2

公开(公告)日：2021-10-26

申请号：US16405165

申请日：2019-05-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Hung Cheng ,  Cheng-Ta Wu ,  Ming-Che Yang ,  Wei-Kung Tsai ,  Yong-En Syu ,  Yeur-Luen Tu ,  Chris Chen

IPC: H01L21/762 ,  H01L29/06 ,  H01L29/16 ,  H01L21/84 ,  H01L27/12 ,  H01L21/02 ,  H01L21/311

Abstract: The present disclosure, in some embodiments, relates to a silicon on insulator (SOI) substrate. The SOI substrate includes a dielectric layer disposed over a first substrate. The dielectric layer has an outside edge aligned with an outside edge of the first substrate. An active layer covers a first annular portion of an upper surface of the dielectric layer. The upper surface of the dielectric layer has a second annular portion that surrounds the first annular portion and extends to the outside edge of the dielectric layer. The second annular portion is uncovered by the active layer.

公开(公告)号：US10529863B2

公开(公告)日：2020-01-07

申请号：US16230025

申请日：2018-12-21

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Cheng-Ta Wu ,  Cheng-Wei Chen ,  Shiu-Ko Jangjian ,  Ting-Chun Wang

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/08 ,  H01L29/16 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66

Abstract: Operations in fabricating a Fin FET include providing a substrate having a fin structure, where an upper portion of the fin structure has a first fin surface profile. An isolation region is formed on the substrate and in contact with the fin structure. A portion of the isolation region is recessed by an etch process to form a recessed portion and to expose the upper portion of the fin structure, where the recessed portion has a first isolation surface profile. A thermal hydrogen treatment is applied to the fin structure and the recessed portion. A gate dielectric layer is formed with a substantially uniform thickness over the fin structure, where the recessed portion is adjusted from the first isolation surface profile to a second isolation surface profile and the fin structure is adjusted from the first fin surface profile to a second fin surface profile, by the thermal hydrogen treatment.

公开(公告)号：US10304723B1

公开(公告)日：2019-05-28

申请号：US15904915

申请日：2018-02-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Hung Cheng ,  Cheng-Ta Wu ,  Ming-Che Yang ,  Wei-Kung Tsai ,  Yong-En Syu ,  Yeur-Luen Tu ,  Chris Chen

IPC: H01L21/762 ,  H01L29/06 ,  H01L29/16 ,  H01L27/12 ,  H01L21/84

Abstract: The present disclosure, in some embodiments, relates to a method of forming an SOI substrate. The method may be performed by epitaxially forming a silicon-germanium (SiGe) layer over a sacrificial substrate and epitaxially forming a first active layer on the SiGe layer. The first active layer has a composition different than the SiGe layer. The sacrificial substrate and is flipped and the first active layer is bonded to an upper surface of a dielectric layer formed over a first substrate. The sacrificial substrate and the SiGe layer are removed and the first active layer is etched to define outermost sidewalls and to expose an outside edge of an upper surface of the dielectric layer. A contiguous active layer is formed by epitaxially forming a second active layer on the first active layer. The first active layer and the second active layer have a substantially same composition.

公开(公告)号：US10164095B2

公开(公告)日：2018-12-25

申请号：US14805450

申请日：2015-07-21

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Cheng-Ta Wu ,  Ting-Chun Wang ,  Wei-Ming You ,  J. W. Wu

IPC: H01L29/78 ,  H01L29/417 ,  H01L29/66 ,  H01L29/06 ,  H01L21/265 ,  H01L21/324

Abstract: A method for manufacturing a semiconductor device is provided including forming one or more fins over a substrate and forming an isolation insulating layer over the one or more fins. A dopant is introduced into the isolation insulating layer. The isolation insulating layer containing the dopant is annealed, and a portion of the oxide layer is removed so as to expose a portion of the fins.