公开(公告)号：US20220359693A1

公开(公告)日：2022-11-10

申请号：US17814725

申请日：2022-07-25

Applicant: Taiwan Semiconductor Manufacturing Co.,Ltd.

Inventor： Guan-Ren Wang ,  Yun-Min Chang ,  Yu-Lien Huang ,  Ching-Feng Fu

IPC: H01L29/423 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/78

Abstract: A semiconductor device including source/drain contacts extending into source/drain regions, below topmost surfaces of the source/drain regions, and methods of forming the same are disclosed. In an embodiment, a semiconductor device includes a semiconductor substrate; a first channel region over the semiconductor substrate; a first gate stack over the semiconductor substrate and surrounding four sides of the first channel region; a first epitaxial source/drain region adjacent the first gate stack and the first channel region; and a first source/drain contact coupled to the first epitaxial source/drain region, a bottommost surface of the first source/drain contact extending below a topmost surface of the first channel region.

公开(公告)号：US20220093757A1

公开(公告)日：2022-03-24

申请号：US17134830

申请日：2020-12-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Lien Huang ,  Ching-Feng Fu ,  Huan-Just Lin

IPC: H01L29/417 ,  H01L29/423 ,  H01L27/088 ,  H01L21/8234

Abstract: In some embodiments, the present disclosure relates to an integrated circuit device. A transistor structure is disposed over a substrate and includes a pair of source/drain regions and a gate electrode between the pair of source/drain regions. A lower inter-layer dielectric (ILD) layer is disposed over the pair of source/drain regions and surrounds the gate electrode. The gate electrode is recessed from top of the lower ILD layer. A gate capping layer is disposed on the gate electrode. The gate capping layer has a top surface aligned or coplanar with that of the lower ILD layer.

公开(公告)号：US20210376139A1

公开(公告)日：2021-12-02

申请号：US16889028

申请日：2020-06-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Lien Huang ,  Guan-Ren Wang ,  Ching-Feng Fu

IPC: H01L29/78 ,  H01L29/417 ,  H01L29/49 ,  H01L29/66 ,  H01L21/8238 ,  H01L21/8234

Abstract: In an embodiment, a structure includes: a gate stack over a channel region of a substrate; a source/drain region adjacent the channel region; a first inter-layer dielectric (ILD) layer over the source/drain region; a silicide between the first ILD layer and the source/drain region, the silicide contacting a top surface of the source/drain region and a bottom surface of the source/drain region; and a first source/drain contact having a first portion and a second portion, the first portion of the first source/drain contact disposed between the silicide and the first ILD layer, the second portion of the first source/drain contact extending through the first ILD layer and contacting the silicide.

公开(公告)号：US20210225707A1

公开(公告)日：2021-07-22

申请号：US17227056

申请日：2021-04-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Chan Yen ,  Ching-Feng Fu ,  Chia-Ying Lee

IPC: H01L21/768 ,  H01L21/8234 ,  H01L23/485 ,  H01L23/522

Abstract: An integrated circuit structure includes a first Inter-Layer Dielectric (ILD), a gate stack in the first ILD, a second ILD over the first ILD, a contact plug in the second ILD, and a dielectric protection layer on opposite sides of, and in contact with, the contact plug. The contact plug and the dielectric protection layer are in the second ILD. A dielectric capping layer is over and in contact with the contact plug.

公开(公告)号：US20200075421A1

公开(公告)日：2020-03-05

申请号：US16536913

申请日：2019-08-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： I-Wen Wu ,  Chen-Ming Lee ,  Fu-Kai Yang ,  Mei-Yun Wang ,  Chang-Yun Chang ,  Ching-Feng Fu ,  Peng Wang

IPC: H01L21/8234 ,  H01L21/768 ,  H01L29/78 ,  H01L23/522 ,  H01L29/417

Abstract: A method includes providing a structure having first and second fins over a substrate and oriented lengthwise generally along a first direction and source/drain (S/D) features over the first and second fins; forming an interlayer dielectric (ILD) layer covering the S/D features; performing a first etching process at least to an area between the S/D features, thereby forming a trench in the ILD layer; depositing a dielectric material in the trench; performing a second etching process to selectively recess the dielectric material; and performing a third etching process to selectively recess the ILD layer, thereby forming a contact hole that exposes the S/D features.

公开(公告)号：US09412656B2

公开(公告)日：2016-08-09

申请号：US14180460

申请日：2014-02-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ching-Feng Fu ,  Yu-Chan Yen ,  Chia-Ying Lee

IPC: H01L21/32 ,  H01L21/44 ,  H01L21/768 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L21/3105 ,  H01L29/78 ,  H01L29/165

CPC classification number: H01L29/41783 ,  H01L21/02532 ,  H01L21/02592 ,  H01L21/31055 ,  H01L21/31111 ,  H01L21/32115 ,  H01L21/76879 ,  H01L21/76897 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/267 ,  H01L29/4175 ,  H01L29/42364 ,  H01L29/45 ,  H01L29/66545 ,  H01L29/66606 ,  H01L29/66795 ,  H01L29/6681 ,  H01L29/78 ,  H01L29/7848 ,  H01L29/7851

Abstract: Some embodiments of the present disclosure relate to a method to form a source/drain self-aligned contact to a transistor or other semiconductor device. The method comprises forming a pair of gate structures over a substrate, and forming a source/drain region between the pair of gate structures. The method further comprises forming a sacrificial source/drain contact which is arranged over the source/drain region and which is arranged laterally between neighboring sidewalls of the pair of gate structures. The method further comprises forming a dielectric layer which extends over the sacrificial source/drain contact and over the pair of gate structures. The dielectric layer differs from the sacrificial source/drain contact. The method further comprises removing a portion of the dielectric layer over the sacrificial source/drain contact and subsequently removing the sacrificial source/drain contact to form a recess, and filling the recess with a conductive material to form a source/drain contact.

Abstract translation: 本公开的一些实施例涉及用于形成与晶体管或其它半导体器件的源极/漏极自对准接触的方法。 该方法包括在衬底上形成一对栅极结构，并且在该对栅极结构之间形成源极/漏极区域。 该方法还包括形成牺牲源极/漏极接触件，该接触件布置在源极/漏极区域之上，并且横向设置在该对栅极结构的相邻侧壁之间。 所述方法还包括形成在所述牺牲源极/漏极接触件上方并在所述一对栅极结构上延伸的介电层。 电介质层与牺牲源极/漏极接触不同。 该方法还包括在牺牲源极/漏极接触件上去除介电层的一部分，随后去除牺牲源极/漏极接触以形成凹陷，并用导电材料填充凹部以形成源极/漏极接触。

公开(公告)号：US20150364575A1

公开(公告)日：2015-12-17

申请号：US14835958

申请日：2015-08-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Harry-Hak-Lay Chuang ,  Bao-Ru Young ,  Wei Cheng Wu ,  Kong-Pin Chang ,  Chia Ming Liang ,  Meng-Fang Hsu ,  Ching-Feng Fu ,  Shih-Ting Hung

IPC: H01L29/66 ,  H01L21/762 ,  H01L21/8234

CPC classification number: H01L29/0649 ,  H01L21/76224 ,  H01L21/823431 ,  H01L21/823481 ,  H01L27/0886 ,  H01L29/66651 ,  H01L29/7833 ,  H01L29/7851

Abstract: Some embodiments of the present disclosure relate to a method. In this method, a semiconductor substrate, which has an active region disposed in the semiconductor substrate, is received. A shallow trench isolation (STI) structure is formed to laterally surround the active region. An upper surface of the active region bounded by the STI structure is recessed to below an upper surface of the STI structure. The recessed upper surface extends continuously between inner sidewalls of the STI structure and leaves upper portions of the inner sidewalls of the STI structure exposed. A semiconductor layer is epitaxially grown on the recessed surface of the active region between the inner sidewalls of the STI structure. A gate dielectric is formed over the epitaxially-grown semiconductor layer. A conductive gate electrode is formed over the gate dielectric.

Abstract translation: 本公开的一些实施例涉及一种方法。 在该方法中，接收具有设置在半导体衬底中的有源区的半导体衬底。 形成浅沟槽隔离（STI）结构以横向围绕有源区域。 由STI结构限定的有源区的上表面凹入到STI结构的上表面的下方。 凹陷的上表面在STI结构的内侧壁之间连续延伸，并且使STI结构的内侧壁的上部露出。 在STI结构的内侧壁之间的有源区的凹面上外延生长半导体层。 在外延生长的半导体层上形成栅极电介质。 在栅极电介质上形成导电栅电极。

公开(公告)号：US20150235897A1

公开(公告)日：2015-08-20

申请号：US14180460

申请日：2014-02-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ching-Feng Fu ,  Yu-Chan Yen ,  Chia-Ying Lee

IPC: H01L21/768 ,  H01L29/417 ,  H01L29/40 ,  H01L21/32 ,  H01L21/4757

CPC classification number: H01L29/41783 ,  H01L21/02532 ,  H01L21/02592 ,  H01L21/31055 ,  H01L21/31111 ,  H01L21/32115 ,  H01L21/76879 ,  H01L21/76897 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/267 ,  H01L29/4175 ,  H01L29/42364 ,  H01L29/45 ,  H01L29/66545 ,  H01L29/66606 ,  H01L29/66795 ,  H01L29/6681 ,  H01L29/78 ,  H01L29/7848 ,  H01L29/7851

Abstract: Some embodiments of the present disclosure relate to a method to form a source/drain self-aligned contact to a transistor or other semiconductor device. The method comprises forming a pair of gate structures over a substrate, and forming a source/drain region between the pair of gate structures. The method further comprises forming a sacrificial source/drain contact which is arranged over the source/drain region and which is arranged laterally between neighboring sidewalls of the pair of gate structures. The method further comprises forming a dielectric layer which extends over the sacrificial source/drain contact and over the pair of gate structures. The dielectric layer differs from the sacrificial source/drain contact. The method further comprises removing a portion of the dielectric layer over the sacrificial source/drain contact and subsequently removing the sacrificial source/drain contact to form a recess, and filling the recess with a conductive material to form a source/drain contact.

Abstract translation: 本公开的一些实施例涉及用于形成与晶体管或其它半导体器件的源极/漏极自对准接触的方法。 该方法包括在衬底上形成一对栅极结构，并且在该对栅极结构之间形成源极/漏极区域。 该方法还包括形成牺牲源极/漏极接触件，该接触件布置在源极/漏极区域之上，并且横向设置在该对栅极结构的相邻侧壁之间。 所述方法还包括形成在所述牺牲源极/漏极接触件上方并在所述一对栅极结构上延伸的介电层。 电介质层与牺牲源极/漏极接触不同。 该方法还包括在牺牲源极/漏极接触件上去除介电层的一部分，随后去除牺牲源极/漏极接触以形成凹陷，并用导电材料填充凹部以形成源极/漏极接触。

公开(公告)号：US20250120113A1

公开(公告)日：2025-04-10

申请号：US18983802

申请日：2024-12-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ching-Feng Fu ,  Guan-Ren Wang ,  Yun-Min Chang ,  Yu-Lien Huang

IPC: H01L29/78 ,  H01L21/768 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/66

Abstract: A semiconductor device and method of manufacture are provided which help to support contacts while material is removed to form air gaps. In embodiments a contact is formed with an enlarged base to help support overlying portions of the contact. In other embodiments a scaffold material may also be placed prior to the formation of the air gaps in order to provide additional support.

公开(公告)号：US20240371645A1

公开(公告)日：2024-11-07

申请号：US18777198

申请日：2024-07-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Lien Huang ,  Guan-Ren Wang ,  Ching-Feng Fu

IPC: H01L21/285 ,  H01L21/02 ,  H01L21/48

Abstract: An embodiment method includes: forming a gate stack over a channel region; growing a source/drain region adjacent the channel region; depositing a first ILD layer over the source/drain region and the gate stack; forming a source/drain contact through the first ILD layer to physically contact the source/drain region; forming a gate contact through the first ILD layer to physically contact the gate stack; performing an etching process to partially expose a first sidewall and a second sidewall, the first sidewall being at a first interface of the source/drain contact and the first ILD layer, the second sidewall being at a second interface of the gate contact and the first ILD layer; forming a first conductive feature physically contacting the first sidewall and a first top surface of the source/drain contact; and forming a second conductive feature physically contacting the second sidewall and a second top surface of the gate contact.