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公开(公告)号：US11785862B2
公开(公告)日：2023-10-10
申请号：US17319590
申请日：2021-05-13
CPC分类号： H10N50/80 , H10B61/22 , H10B63/30 , H10N50/01 , H10N70/063 , H10N70/826
摘要： A memory cell with dual sidewall spacers and its manufacturing methods are provided. In some embodiments, the memory cell includes a bottom electrode disposed over a substrate, a resistance switching dielectric disposed over the bottom electrode and having a variable resistance, and a top electrode disposed over the resistance switching dielectric. The memory cell further includes a first sidewall spacer disposed on an upper surface of the bottom electrode and extending upwardly alongside the resistance switching dielectric and the top electrode. The memory cell further includes a second sidewall spacer having a bottom surface disposed on the upper surface of the bottom electrode and directly and conformally lining the first sidewall spacer.
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公开(公告)号：US11683990B2
公开(公告)日：2023-06-20
申请号：US16717115
申请日：2019-12-17
摘要： Some embodiments relate to an integrated circuit including a semiconductor substrate and an interconnect structure disposed over the semiconductor substrate. The interconnect structure includes a plurality of dielectric layers and a plurality of metal layers that are stacked over one another in alternating fashion. The plurality of metal layers include a lower metal layer and an upper metal layer disposed over the lower metal layer. A bottom electrode is disposed over and in electrical contact with the lower metal layer. A dielectric layer is disposed over an upper surface of the bottom electrode. A top electrode is disposed over an upper surface of the dielectric layer and is in direct electrical contact with a lower surface of the upper metal layer.
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公开(公告)号：US11322543B2
公开(公告)日：2022-05-03
申请号：US16884353
申请日：2020-05-27
摘要： Various embodiments of the present disclosure are directed towards a memory device including a protective sidewall spacer layer that laterally encloses a memory cell. An upper inter-level dielectric (ILD) layer overlying a substrate. The memory cell is disposed with the upper ILD layer. The memory cell includes a top electrode, a bottom electrode, and a magnetic tunnel junction (MTJ) structure disposed between the top and bottom electrodes. A sidewall spacer structure laterally surrounds the memory cell. The sidewall spacer structure includes a first sidewall spacer layer, a second sidewall spacer layer, and the protective sidewall spacer layer. The first and second sidewall spacer layers comprise a first material and the protective sidewall spacer layer comprises a second material different from the first material. A conductive wire overlying the first memory cell. The conductive wire contacts the top electrode and the protective sidewall spacer layer.
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公开(公告)号：US11316096B2
公开(公告)日：2022-04-26
申请号：US16899700
申请日：2020-06-12
发明人： Harry-Hak-Lay Chuang , Hung Cho Wang , Tong-Chern Ong , Wen-Ting Chu , Yu-Wen Liao , Kuei-Hung Shen , Kuo-Yuan Tu , Sheng-Huang Huang
摘要： The present disclosure relates to an integrated circuit. The integrated circuit includes a an inter-layer dielectric (ILD) structure laterally surrounding a conductive interconnect. A dielectric protection layer is disposed over the ILD structure and a passivation layer is disposed over the dielectric protection layer. The passivation layer includes a protrusion extending outward from an upper surface of the passivation layer. A bottom electrode continuously extends from over the passivation layer to between sidewalls of the passivation layer. A data storage element is over the bottom electrode and a top electrode is over the data storage element.
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公开(公告)号：US11264561B2
公开(公告)日：2022-03-01
申请号：US16809998
申请日：2020-03-05
发明人： Ming-Che Ku , Jun-Yao Chen , Sheng-Huang Huang , Jiun-Yu Tsai , Harry-Hak-Lay Chuang , Hung-Cho Wang
摘要： A method of forming a magnetic random access memory (MRAM) device includes forming a bottom electrode layer over a substrate including an inter-metal dielectric (IMD) layer having a metal line therein; forming a barrier layer over the bottom electrode layer; forming a magnetic tunnel junction (MTJ) layer stack over the bottom electrode layer; forming a dielectric layer over the MTJ layer stack; forming an opening in the dielectric layer to expose the barrier layer; filling the opening in the dielectric layer with a top electrode; after filling the opening in the dielectric layer with the top electrode, etching the dielectric layer to expose the barrier layer; and patterning the MTJ layer stack to form an MTJ stack that exposes the bottom electrode layer.
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公开(公告)号：US11244983B2
公开(公告)日：2022-02-08
申请号：US16893010
申请日：2020-06-04
发明人： Harry-Hak-Lay Chuang , Wen-Chun You , Hung Cho Wang , Yen-Yu Shih
摘要： The present disclosure provides a system and method for forming a reduced area MRAM memory cell including a substrate, a transistor overlying the substrate and a magnetic tunnel junction overlying the transistor. The transistor includes a first and second source regions, a drain region between the first and second source regions, at least one first channel region between the drain region and the first source region, at least one second channel region between the drain region and the second source region, a first gate structure overlying the at least one first channel region, and a second gate structure overlying the at least one second channel region. First and second metal layers overlie the transistor. The first and second metal layers are configured to couple a common source line signal to the first and second source regions.
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公开(公告)号：US20210375987A1
公开(公告)日：2021-12-02
申请号：US16884353
申请日：2020-05-27
摘要： Various embodiments of the present disclosure are directed towards a memory device including a protective sidewall spacer layer that laterally encloses a memory cell. An upper inter-level dielectric (ILD) layer overlying a substrate. The memory cell is disposed with the upper ILD layer. The memory cell includes a top electrode, a bottom electrode, and a magnetic tunnel junction (MTJ) structure disposed between the top and bottom electrodes. A sidewall spacer structure laterally surrounds the memory cell. The sidewall spacer structure includes a first sidewall spacer layer, a second sidewall spacer layer, and the protective sidewall spacer layer. The first and second sidewall spacer layers comprise a first material and the protective sidewall spacer layer comprises a second material different from the first material. A conductive wire overlying the first memory cell. The conductive wire contacts the top electrode and the protective sidewall spacer layer.
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公开(公告)号：US11145806B2
公开(公告)日：2021-10-12
申请号：US16889395
申请日：2020-06-01
IPC分类号： H01L43/02 , H01L43/08 , H01L27/22 , H01L43/12 , H01L21/302
摘要： A device includes a plurality of bottom electrode features, a plurality of Magnetic Tunnel Junction (MTJ) stacks formed on top surfaces of the bottom electrode features, top electrode features formed on top of the MTJ stacks, and an etch stop layer extending along side surfaces of the bottom electrode feature and partially along side surfaces of the MTJ stacks.
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公开(公告)号：US11005032B2
公开(公告)日：2021-05-11
申请号：US16711626
申请日：2019-12-12
摘要： Some embodiments relate to a method for manufacturing a magnetoresistive random-access memory (MRAM) cell. The method includes forming a spacer layer surrounding at least a magnetic tunnel junction (MTJ) layer and a top electrode of the MRAM cell; etching the spacer layer to expose a top surface of the top electrode and a top surface of a spacer formed by the spacer layer; forming an upper etch stop layer over the top electrode top surface and the spacer top surface; and forming an upper metal layer in contact with the top electrode top surface of the MRAM cell. A width of the upper etch stop layer is greater than a width of a bottom surface of the upper metal layer.
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公开(公告)号：US20210111333A1
公开(公告)日：2021-04-15
申请号：US16601723
申请日：2019-10-15
发明人： Yao-Wen Chang , Chung-Chiang Min , Harry-Hak-Lay Chuang , Hung Cho Wang , Tsung-Hsueh Yang , Yuan-Tai Tseng , Sheng-Huang Huang , Chia-Hua Lin
摘要： Various embodiments of the present disclosure are directed towards an integrated chip including a magnetoresistive random access memory (MRAM) cell over a substrate. A dielectric structure overlies the substrate. The MRAM cell is disposed within the dielectric structure. The MRAM cell includes a magnetic tunnel junction (MTJ) sandwiched between a bottom electrode and a top electrode. A conductive wire overlies the top electrode. A sidewall spacer structure continuously extends along a sidewall of the MTJ and the top electrode. The sidewall spacer structure includes a first sidewall spacer layer, a second sidewall spacer layer, and a protective sidewall spacer layer sandwiched between the first and second sidewall spacer layers. The first and second sidewall spacer layers comprise a first material and the protective sidewall spacer layer comprises a second material different than the first material.
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