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    MRAM memory cell layout for minimizing bitcell area
    34.
    发明授权
    MRAM memory cell layout for minimizing bitcell area 有权

    公开(公告)号：US11800724B2

    公开(公告)日：2023-10-24

    申请号：US17562949

    申请日：2021-12-27

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Harry-Hak-Lay Chuang ,  Wen-Chun You ,  Hung Cho Wang ,  Yen-Yu Shih

    IPC: H10B61/00 ,  H10N50/01 ,  H10N50/80

    CPC classification number: H10B61/22 ,  H10N50/01 ,  H10N50/80

    Abstract: An MRAM memory cell includes a substrate and a transistor. The transistor includes: first and second source regions; a drain region between the first and second source regions; a first channel region between the drain region and the first source region; a second channel region between the drain region and the second source region; a first gate structure over the first channel region; and a second gate structure over the second channel region. A magnetic tunnel junction is overlying the transistor. The drain region is coupled to the magnetic tunnel junction. A first metal layer is overlying the transistor, and a second metal layer is overlying the first metal layer. The second and first metal layers couple a common source line signal to the first and second source regions of the MRAM memory cell and to those of a neighboring MRAM memory cell.

    Techniques for MRAM MTJ top electrode connection
    36.
    发明授权
    Techniques for MRAM MTJ top electrode connection 有权

    公开(公告)号：US11683990B2

    公开(公告)日：2023-06-20

    申请号：US16717115

    申请日：2019-12-17

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Harry-Hak-Lay Chuang ,  Chern-Yow Hsu ,  Shih-Chang Liu

    IPC: H01L43/08 ,  H10N50/10 ,  H10N50/01 ,  H10B61/00

    CPC classification number: H10N50/10 ,  H10N50/01 ,  H10B61/22

    Abstract: Some embodiments relate to an integrated circuit including a semiconductor substrate and an interconnect structure disposed over the semiconductor substrate. The interconnect structure includes a plurality of dielectric layers and a plurality of metal layers that are stacked over one another in alternating fashion. The plurality of metal layers include a lower metal layer and an upper metal layer disposed over the lower metal layer. A bottom electrode is disposed over and in electrical contact with the lower metal layer. A dielectric layer is disposed over an upper surface of the bottom electrode. A top electrode is disposed over an upper surface of the dielectric layer and is in direct electrical contact with a lower surface of the upper metal layer.

    Method for MRAM top electrode connection
    37.
    发明授权
    Method for MRAM top electrode connection 有权

    公开(公告)号：US11322543B2

    公开(公告)日：2022-05-03

    申请号：US16884353

    申请日：2020-05-27

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Harry-Hak-Lay Chuang ,  Hung Cho Wang ,  Sheng-Chang Chen ,  Sheng-Huang Huang

    IPC: H01L27/22 ,  H01L43/02 ,  H01L43/12

    Abstract: Various embodiments of the present disclosure are directed towards a memory device including a protective sidewall spacer layer that laterally encloses a memory cell. An upper inter-level dielectric (ILD) layer overlying a substrate. The memory cell is disposed with the upper ILD layer. The memory cell includes a top electrode, a bottom electrode, and a magnetic tunnel junction (MTJ) structure disposed between the top and bottom electrodes. A sidewall spacer structure laterally surrounds the memory cell. The sidewall spacer structure includes a first sidewall spacer layer, a second sidewall spacer layer, and the protective sidewall spacer layer. The first and second sidewall spacer layers comprise a first material and the protective sidewall spacer layer comprises a second material different from the first material. A conductive wire overlying the first memory cell. The conductive wire contacts the top electrode and the protective sidewall spacer layer.

    MRAM memory cell layout for minimizing bitcell area
    40.
    发明授权
    MRAM memory cell layout for minimizing bitcell area 有权

    公开(公告)号：US11244983B2

    公开(公告)日：2022-02-08

    申请号：US16893010

    申请日：2020-06-04

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Harry-Hak-Lay Chuang ,  Wen-Chun You ,  Hung Cho Wang ,  Yen-Yu Shih

    IPC: H01L27/22 ,  H01L43/02 ,  H01L43/12

    Abstract: The present disclosure provides a system and method for forming a reduced area MRAM memory cell including a substrate, a transistor overlying the substrate and a magnetic tunnel junction overlying the transistor. The transistor includes a first and second source regions, a drain region between the first and second source regions, at least one first channel region between the drain region and the first source region, at least one second channel region between the drain region and the second source region, a first gate structure overlying the at least one first channel region, and a second gate structure overlying the at least one second channel region. First and second metal layers overlie the transistor. The first and second metal layers are configured to couple a common source line signal to the first and second source regions.

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