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    Spacer-defined back-end transistor as memory selector
    31.
    发明授权
    Spacer-defined back-end transistor as memory selector 有权

    公开(公告)号：US11309353B2

    公开(公告)日：2022-04-19

    申请号：US17078583

    申请日：2020-10-23

    申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

    发明人： Ken-Ichi Goto ,  Chung-Te Lin ,  Mauricio Manfrini

    IPC分类号： H01L27/24 ,  H01L27/22

    摘要： The present disclosure, in some embodiments, relates to a memory device. In some embodiments, the memory device comprises a substrate and an interconnect structure disposed over the substrate. The interconnect structure comprises stacked interconnect metal layers disposed within stacked interlayer dielectric (ILD) layers. A memory cell is disposed between an upper interconnect metal layer and an intermediate interconnect metal layer. A selecting transistor is connected to the memory cell and disposed between the intermediate interconnect metal layer and a lower interconnect metal layer. By placing the selecting transistor within the back-end interconnect structure between two interconnect metal layers, front-end space is saved, and more integration flexibility is provided.

    SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
    32.
    发明申请
    SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF 有权

    公开(公告)号：US20220013580A1

    公开(公告)日：2022-01-13

    申请号：US16924162

    申请日：2020-07-08

    申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

    发明人： Mauricio MANFRINI ,  Chung-Te Lin ,  Ken-Ichi Goto

    IPC分类号： H01L27/22 ,  H01L43/02 ,  H01L43/08 ,  H01L43/12 ,  H01L43/10 ,  H01L29/423 ,  H01L23/528

    摘要： A semiconductor device includes a semiconductor substrate and an interconnection region disposed on the semiconductor substrate. The interconnection region includes stacked metallization levels, a magnetic tunnel junction, and a transistor. The magnetic tunnel junction is formed on a first conductive pattern of a first metallization level of the stacked metallization levels. The transistor is formed on a second conductive pattern of a second metallization level of the stacked metallization levels. The transistor is a vertical gate-all-around transistor. A drain contact of the transistor is electrically connected to the magnetic tunnel junction by the first conductive pattern of the first metallization level. The second metallization level is closer to the semiconductor substrate than the first metallization level.

    Method of manufacturing a semiconductor device and a semiconductor device
    33.
    发明授权
    Method of manufacturing a semiconductor device and a semiconductor device 有权

    公开(公告)号：US10193090B2

    公开(公告)日：2019-01-29

    申请号：US15627722

    申请日：2017-06-20

    申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

    发明人： Chun-Chieh Lu ,  Jean-Pierre Colinge ,  Ken-Ichi Goto ,  Zhiqiang Wu ,  Yu-Ming Lin

    IPC分类号： H01L51/05 ,  H01L51/00 ,  H01L51/10

    摘要： In a method of manufacturing a gate-all-around field effect transistor, a trench is formed over a substrate. Nano-tube structures are arranged into the trench, each of which includes a carbon nanotube (CNT) having a gate dielectric layer wrapping around the CNT and a gate electrode layer over the gate dielectric layer. An anchor layer is formed in the trench. A part of the anchor layer is removed at a source/drain (S/D) region. The gate electrode layer and the gate dielectric layer are removed at the S/D region, thereby exposing a part of the CNT at the S/D region. An S/D electrode layer is formed on the exposed part of the CNT. A part of the anchor layer is removed at a gate region, thereby exposing a part of the gate electrode layer of the gate structure. A gate contact layer is formed on the exposed part of the gate electrode layer.

    TRANSISTOR DESIGN
    40.
    发明申请
    TRANSISTOR DESIGN 有权
    晶体管设计

    公开(公告)号：US20150200253A1

    公开(公告)日：2015-07-16

    申请号：US14156546

    申请日：2014-01-16

    申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

    发明人： Wen-Yuan Chen ,  Tsung-Hsing Yu ,  Ken-Ichi Goto ,  Zhiqiang Wu

    IPC分类号： H01L29/10 ,  H01L29/66 ,  H01L29/417 ,  H01L29/167 ,  H01L29/16 ,  H01L29/165 ,  H01L21/02 ,  H01L21/265 ,  H01L29/78 ,  H01L29/36

    CPC分类号： H01L29/1054 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/26513 ,  H01L21/26586 ,  H01L21/76224 ,  H01L29/0653 ,  H01L29/105 ,  H01L29/1083 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/165 ,  H01L29/167 ,  H01L29/365 ,  H01L29/41725 ,  H01L29/66477 ,  H01L29/66492 ,  H01L29/6659 ,  H01L29/66651 ,  H01L29/78 ,  H01L29/7833

    摘要： Some embodiments of the present disclosure relate to a transistor device formed in a semiconductor substrate containing dopant impurities of a first impurity type. The transistor device includes channel composed of a delta-doped layer comprising dopant impurities of the first impurity type, and configured to produce a peak dopant concentration within the channel. The channel further includes a layer of carbon-containing material overlying the delta-doped layer, and configured to prevent back diffusion of dopants from the delta-doped layer and semiconductor substrate. The channel also includes of a layer of substrate material overlying the layer of carbon-containing material, and configured to achieve steep retrograde dopant concentration profile a near a surface of the channel. In some embodiments, a counter-doped layer underlies the delta-doped layer configured to reduce leakage within the semiconductor substrate, and includes dopant impurities of a second impurity type, which is opposite the first impurity type.

    摘要翻译： 本公开的一些实施例涉及形成在包含第一杂质类型的掺杂杂质的半导体衬底中的晶体管器件。 该晶体管器件包括由包括第一杂质类型的掺杂杂质的δ掺杂层构成的沟道，并且被配置为在沟道内产生峰值掺杂剂浓度。 通道还包括覆盖在δ掺杂层上的含碳材料层，并且被配置为防止掺杂剂从δ-掺杂层和半导体衬底的反向扩散。 通道还包括覆盖在含碳材料层上的衬底材料层，并且被配置为在通道的表面附近实现陡峭的逆向掺杂剂浓度分布。 在一些实施例中，反掺杂层位于配置成减少半导体衬底内的泄漏的δ掺杂层的下面，并且包括与第一杂质类型相反的第二杂质类型的掺杂杂质。