公开(公告)号：US12243783B2

公开(公告)日：2025-03-04

申请号：US17232898

申请日：2021-04-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hui-Lin Huang ,  Li-Li Su ,  Yee-Chia Yeo ,  Chii-Horng Li

IPC: H01L21/8238 ,  H01L21/02 ,  H01L21/033 ,  H01L21/285 ,  H01L27/092 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/45 ,  H01L29/66 ,  H01L29/786

Abstract: A method includes etching a first recess adjacent a first dummy gate stack and a first fin; etching a second recess adjacent a second dummy gate stack and a second fin; and epitaxially growing a first epitaxy region in the first recess. The method further includes depositing a first metal-comprising mask over the first dummy gate stack, over the second dummy gate stack, over the first epitaxy region in the first recess, and in the second recess; patterning the first metal-comprising mask to expose the first dummy gate stack and the first epitaxy region; epitaxially growing a second epitaxy region in the first recess over the first epitaxy region; and after epitaxially growing the second epitaxy region, removing remaining portions of the first metal-comprising mask.

公开(公告)号：US12154974B2

公开(公告)日：2024-11-26

申请号：US18521556

申请日：2023-11-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Chiang Chang ,  Ming-Hua Yu ,  Li-Li Su

IPC: H01L29/66 ,  H01L21/20 ,  H01L21/8234 ,  H01L27/092 ,  H01L29/417 ,  H01L29/78

Abstract: A method includes forming a first semiconductor fin and a second semiconductor fin in an n-type Fin Field-Effect (FinFET) region and a p-type FinFET region, respectively, forming a first dielectric fin and a second dielectric fin in the n-type FinFET region and the p-type FinFET region, respectively, forming a first epitaxy mask to cover the second semiconductor fin and the second dielectric fin, performing a first epitaxy process to form an n-type epitaxy region based on the first semiconductor fin, removing the first epitaxy mask, forming a second epitaxy mask to cover the n-type epitaxy region and the first dielectric fin, performing a second epitaxy process to form a p-type epitaxy region based on the second semiconductor fin, and removing the second epitaxy mask. After the second epitaxy mask is removed, a portion of the second epitaxy mask is left on the first dielectric fin.

公开(公告)号：US20240387629A1

公开(公告)日：2024-11-21

申请号：US18786808

申请日：2024-07-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei-Min Liu ,  Li-Li Su ,  Chii-Horng Li ,  Yee-Chia Yeo

IPC: H01L29/06 ,  H01L21/8234 ,  H01L29/423 ,  H01L29/786

Abstract: A device includes a first nanostructure over a semiconductor substrate; a second nanostructure over the first nanostructure; a gate structure surrounding the first nanostructure and the second nanostructure; a first epitaxial region in the semiconductor substrate adjacent the gate structure, wherein the first epitaxial region is a first doped semiconductor material; and a second epitaxial region over the first epitaxial region, wherein the second epitaxial region is adjacent the first nanostructure and the second nanostructure, wherein the second epitaxial region is a second doped semiconductor material that is different from the first doped semiconductor material. In an embodiment, the first doped semiconductor material has a smaller doping concentration than the second doped semiconductor material.

公开(公告)号：US20240379781A1

公开(公告)日：2024-11-14

申请号：US18780151

申请日：2024-07-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei Hao Lu ,  Li-Li Su ,  Chien-I Kuo ,  Yee-Chia Yeo ,  Wei-Yang Lee ,  Yu-Xuan Huang ,  Ching-Wei Tsai ,  Kuan-Lun Cheng

IPC: H01L29/417 ,  H01L21/02 ,  H01L29/06 ,  H01L29/40 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786

Abstract: A semiconductor device, includes a device layer comprising: a channel region; a gate stack over and along sidewalls of the channel region and a first insulating fin; and an epitaxial source/drain region adjacent the channel region, wherein the epitaxial source/drain region extends through the first insulating fin. The semiconductor device further includes a front-side interconnect structure on a first side of the device layer; and a backside interconnect structure on a second side of the device layer opposite the first side of the device layer. The backside interconnect structure comprises a backside source/drain contact that is electrically connected to the epitaxial source/drain region.

公开(公告)号：US20240379454A1

公开(公告)日：2024-11-14

申请号：US18779272

申请日：2024-07-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hui-Lin Huang ,  Li-Li Su ,  Yee-Chia Yeo ,  Chii-Horng Li

IPC: H01L21/8238 ,  H01L21/02 ,  H01L21/033 ,  H01L21/285 ,  H01L27/092 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/45 ,  H01L29/66 ,  H01L29/786

Abstract: A method includes etching a first recess adjacent a first dummy gate stack and a first fin; etching a second recess adjacent a second dummy gate stack and a second fin; and epitaxially growing a first epitaxy region in the first recess. The method further includes depositing a first metal-comprising mask over the first dummy gate stack, over the second dummy gate stack, over the first epitaxy region in the first recess, and in the second recess; patterning the first metal-comprising mask to expose the first dummy gate stack and the first epitaxy region; epitaxially growing a second epitaxy region in the first recess over the first epitaxy region; and after epitaxially growing the second epitaxy region, removing remaining portions of the first metal-comprising mask.

公开(公告)号：US12132118B2

公开(公告)日：2024-10-29

申请号：US17231183

申请日：2021-04-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei-Min Liu ,  Li-Li Su ,  Yee-Chia Yeo

IPC: H01L29/786 ,  H01L29/06 ,  H01L29/66

CPC classification number: H01L29/78696 ,  H01L29/0665 ,  H01L29/66742

Abstract: Semiconductor devices and methods of fabricating the semiconductor devices are described herein. The method includes steps for patterning fins in a multilayer stack and forming an opening in a fin as an initial step in forming a source/drain region. The opening is formed into a parasitic channel region of the fin. Once the opening has been formed, a first semiconductor material is epitaxially grown at the bottom of the opening to a level over the top of the parasitic channel region. A second semiconductor material is epitaxially grown from the top of the first semiconductor material to fill and/or overfill the opening. The second semiconductor material is differently doped from the first semiconductor material. A stack of nanostructures is formed by removing sacrificial layers of the multilayer stack, the second semiconductor material being electrically coupled to the nanostructures.

公开(公告)号：US20240258429A1

公开(公告)日：2024-08-01

申请号：US18635834

申请日：2024-04-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-An Lin ,  Wei-Yuan Lu ,  Feng-Cheng Yang ,  Tzu-Ching Lin ,  Li-Li Su

IPC: H01L29/78 ,  A61B5/15 ,  G01N1/14 ,  G01N33/49 ,  H01L21/02 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/04 ,  H01L29/66

CPC classification number: H01L29/785 ,  A61B5/150099 ,  A61B5/150992 ,  G01N1/14 ,  G01N33/4915 ,  H01L21/02532 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823878 ,  H01L27/0924 ,  H01L29/66795 ,  H01L29/045 ,  H01L29/7853

Abstract: The present application provides a semiconductor device and the method of making the same. The method includes recessing a fin extending from a substrate, forming a base epitaxial feature on the recessed fin, forming a bar-like epitaxial feature on the base epitaxial feature, and forming a conformal epitaxial feature on the bar-like epitaxial feature. The forming of the bar-like epitaxial feature includes in-situ doping the bar-like epitaxial feature with an n-type dopant at a first doping concentration. The forming of the conformal epitaxial feature includes in-situ doping the conformal epitaxial feature with a second doping concentration greater than the first doping concentration.

公开(公告)号：US11990511B2

公开(公告)日：2024-05-21

申请号：US17458950

申请日：2021-08-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chien-I Kuo ,  Wei Hao Lu ,  Li-Li Su ,  Yee-Chia Yeo

IPC: H01L29/94 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/08 ,  H01L29/66 ,  H01L29/76 ,  H01L29/78

CPC classification number: H01L29/0847 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823481 ,  H01L29/0649 ,  H01L29/66795 ,  H01L29/7851

Abstract: A method of forming a semiconductor includes forming a first recess in a first semiconductor fin protruding from a substrate and forming a second recess in a second semiconductor fin protruding from the substrate first semiconductor fin and forming a source/drain region in the first recess and the second recess. Forming the source/drain region includes forming a first portion of a first layer in the first recess and forming a second portion of the first layer in the second recess, forming a second layer on the first layer by flowing a first precursor, and forming a third layer on the second layer by flowing a second precursor, the third layer being a single continuous material.

公开(公告)号：US20240113205A1

公开(公告)日：2024-04-04

申请号：US18521556

申请日：2023-11-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Chiang Chang ,  Ming-Hua Yu ,  Li-Li Su

IPC: H01L29/66 ,  H01L21/20 ,  H01L21/8234 ,  H01L27/092 ,  H01L29/417 ,  H01L29/78

CPC classification number: H01L29/66795 ,  H01L21/20 ,  H01L21/823431 ,  H01L27/0924 ,  H01L29/41791 ,  H01L29/785

Abstract: A method includes forming a first semiconductor fin and a second semiconductor fin in an n-type Fin Field-Effect (FinFET) region and a p-type FinFET region, respectively, forming a first dielectric fin and a second dielectric fin in the n-type FinFET region and the p-type FinFET region, respectively, forming a first epitaxy mask to cover the second semiconductor fin and the second dielectric fin, performing a first epitaxy process to form an n-type epitaxy region based on the first semiconductor fin, removing the first epitaxy mask, forming a second epitaxy mask to cover the n-type epitaxy region and the first dielectric fin, performing a second epitaxy process to form a p-type epitaxy region based on the second semiconductor fin, and removing the second epitaxy mask. After the second epitaxy mask is removed, a portion of the second epitaxy mask is left on the first dielectric fin.

公开(公告)号：US20230317785A1

公开(公告)日：2023-10-05

申请号：US17712965

申请日：2022-04-04

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yung-Chun Yang ,  Wei Hao Lu ,  Wei-Min Liu ,  Li-Li Su ,  Chii-Horng Li ,  Yee-Chia Yeo

IPC: H01L29/06 ,  H01L29/786 ,  H01L29/66 ,  H01L21/8234

CPC classification number: H01L29/0665 ,  H01L29/78618 ,  H01L29/78696 ,  H01L29/66742 ,  H01L21/823418 ,  H01L21/823412

Abstract: A device includes a first nanostructure over a substrate and a first source/drain region adjacent the first nanostructure. The first source/drain region includes a first epitaxial layer covering a first sidewall of the first nanostructure. The first epitaxial layer has a first concentration of a first dopant. The first epitaxial layer has a round convex profile opposite the first sidewall of the first nanostructure in a cross-sectional view. The first source/drain region further includes a second epitaxial layer covering the round convex profile of the first epitaxial layer in the cross-sectional view. The second epitaxial layer has a second concentration of the first dopant, the second concentration being different from the first concentration.