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    Memory device
    34.
    发明授权
    Memory device 有权

    公开(公告)号：US11423960B2

    公开(公告)日：2022-08-23

    申请号：US17085398

    申请日：2020-10-30

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

    Inventor： Meng-Sheng Chang ,  Chia-En Huang ,  Yi-Ching Liu ,  Yih Wang

    IPC: G11C7/10 ,  G11C8/14 ,  G11C7/18 ,  G11C8/08 ,  G11C7/12

    Abstract: A memory device is disclosed, including a first switch and multiple first memory cells that are arranged in a first column, a second switch and multiple second memory cells that are arranged in a second column, a first data line and a second data line. The first data line is coupled to the first memory cells and the second memory cells. The second data line is coupled connected to the first memory cells and the second memory cells. The first switch transmits a data signal in the first data line in response to a control signal. The second switch outputs the data signal received from the second data line in response to the control signal.

    HIGH-VOLTAGE NANO-SHEET TRANSISTOR
    35.
    发明申请
    HIGH-VOLTAGE NANO-SHEET TRANSISTOR 有权

    公开(公告)号：US20210408234A1

    公开(公告)日：2021-12-30

    申请号：US16916951

    申请日：2020-06-30

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Yu-Xuan Huang ,  Chia-En Huang ,  Ching-Wei Tsai ,  Kuan-Lun Cheng ,  Yih Wang

    IPC: H01L29/06 ,  H01L27/088 ,  H01L27/112 ,  H01L21/8234 ,  H01L29/423 ,  H01L29/78 ,  H01L29/66

    Abstract: The present disclosure is directed to methods for the formation of high-voltage nano-sheet transistors and low-voltage gate-all-around transistors on a common substrate. The method includes forming a fin structure with first and second nano-sheet layers on the substrate. The method also includes forming a gate structure having a first dielectric and a first gate electrode on the fin structure and removing portions of the fin structure not covered by the gate structure. The method further includes partially etching exposed surfaces of the first nano-sheet layers to form recessed portions of the first nano-sheet layers in the fin structure and forming a spacer structure on the recessed portions. In addition, the method includes replacing the first gate electrode with a second dielectric and a second gate electrode, and forming an epitaxial structure abutting the fin structure.

    Test device for memory, method for detecting hardware failure in memory device, and test apparatus of memory array
    36.
    发明授权
    Test device for memory, method for detecting hardware failure in memory device, and test apparatus of memory array 有权

    公开(公告)号：US11183261B2

    公开(公告)日：2021-11-23

    申请号：US16836928

    申请日：2020-04-01

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Hiroki Noguchi ,  Ku-Feng Lin ,  Yih Wang

    IPC: G11C29/00 ,  G11C29/38 ,  G11C29/36 ,  G11C11/16

    Abstract: A testing device for memory includes a memory array and a test apparatus. The test apparatus includes a controller and a pattern generator. The pattern generator generates a background data, a first pattern data, and a second pattern data. The controller sets up the background data to a to-be-tested memory sub-array of the memory sub-arrays, performs a first memory test operation with the to-be-tested memory sub-array according to the first pattern data for detecting an occurrence of a hardware failure of the to-be-tested memory sub-array is occurred during the first memory test operation. The controller performs a second memory test operation with the to-be-tested memory sub-array according to the second pattern data for detecting the occurrence of the hardware failure of the to-be-tested memory sub-array during the second memory test operation in response to the hardware failure of the to-be-tested memory sub-array is not occurred during the first memory test operation.

    MEMORY DEVICE, ACCESS CONTROLLER THEREOF AND METHOD FOR ACCESSING MEMORY DEVICE
    37.
    发明申请
    MEMORY DEVICE, ACCESS CONTROLLER THEREOF AND METHOD FOR ACCESSING MEMORY DEVICE 有权

    公开(公告)号：US20210271479A1

    公开(公告)日：2021-09-02

    申请号：US16923107

    申请日：2020-07-08

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Hiroki Noguchi ,  Yih Wang

    IPC: G06F9/30 ,  G06F11/10

    Abstract: A memory device includes a memory array with at least one memory macro, a flag, and a controller. The controller is coupled to the memory array. Each bit of data stored in the at least one memory macro is presented as a first bit type or a second bit type. The controller is configured to select one of a first situation mode and a second situation mode as a selected situation mode according to a first retention time of the first bit type and a second retention time of the second bit type. The first situation mode is that a number of bits with the first bit type in data is larger than a number of bit with the second bit type in data, and the second situation mode is that the number of bit with the first bit type in data is not larger than the number of bits with the second bit type in data. In a write operation of the at least one memory macro, the controller determines that an input data is meet the selected situation mode or not. In response to the input data is meet the selected situation mode, the controller disables the flag and writes the input data into the at least one memory macro. In response to the input data is not meet the selected situation mode, the controller enables the flag, inverts the input data, and writes an inverted input data into the at least one memory macro.

    MEMORY DEVICE AND SCHEDULING METHOD FOR MEMORY DEVICE
    38.
    发明申请
    MEMORY DEVICE AND SCHEDULING METHOD FOR MEMORY DEVICE 有权

    公开(公告)号：US20210271417A1

    公开(公告)日：2021-09-02

    申请号：US16985240

    申请日：2020-08-05

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Hiroki Noguchi ,  Shih-Lien Linus Lu ,  Yu-Der Chih ,  Yih Wang

    IPC: G06F3/06 ,  G06F9/48 ,  G06F1/28

    Abstract: A memory device including a memory array with a plurality of memory macros, a power supplying circuit, and a controller is provided. The power supplying circuit is coupled to the memory array. The controller is coupled to the memory array. The power supplying circuit is configured to provide power to perform write operations to a number of the memory macros at the same time. The number of the memory macros for the write operations performed at the same time is not higher than a maximum number of the memory macros. The controller obtains the maximum number of the memory macros for the write operations performed at the same time by the power supplying circuit. The controller re-arranges a schedule for a sequence of the write operations of the memory macros to generate a re-arranged schedule. The maximum number is taken as a threshold value. In the re-arranged schedule, a number of part of the memory macros for the write operations performed at the same time is equal to or less then the threshold value.

    METHOD OF MINIMIZING READ-DISTURB-WRITE EFFECT OF SRAM CIRCUIT AND SRAM CIRCUIT THEREOF
    39.
    发明申请
    METHOD OF MINIMIZING READ-DISTURB-WRITE EFFECT OF SRAM CIRCUIT AND SRAM CIRCUIT THEREOF 有权

    公开(公告)号：US20210098035A1

    公开(公告)日：2021-04-01

    申请号：US16876138

    申请日：2020-05-18

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Jui-Che Tsai ,  Chia-En Huang ,  Yu-Hao Hsu ,  Yih Wang

    IPC: G11C7/10 ,  G11C7/12 ,  G11C7/06

    Abstract: In an exemplary embodiment, the disclosure provides a memory circuit which includes a dual port memory cell for storing a binary value accessed through a first port and a second port, a first WL switch connected to the dual port memory cell and controlled by a first WL voltage, a second WL switch connected to the dual port memory cell and controlled by a second WL voltage, a BL connected to the first WL switch for accessing the memory cell through the first port and having a first BL voltage, a second BL connected to the second WL switch for accessing the memory cell through the second port and having a second BL voltage, a BL selection circuit connected to the second WL switch for selecting the second BL, and a BL voltage pull down circuit connected to the BL selection circuit and the second WL switch.

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