公开(公告)号：US20170207117A1

公开(公告)日：2017-07-20

申请号：US15473166

申请日：2017-03-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tsan-Chun WANG ,  De-Wei YU ,  Ziwei FANG ,  Yi-Fan CHEN

IPC: H01L21/768 ,  H01L21/311 ,  H01L21/3105 ,  H01L23/522 ,  H01L27/088 ,  H01L21/8234 ,  H01L21/3115 ,  H01L29/417

CPC classification number: H01L21/76825 ,  H01L21/02321 ,  H01L21/02337 ,  H01L21/265 ,  H01L21/3105 ,  H01L21/31051 ,  H01L21/31111 ,  H01L21/31155 ,  H01L21/324 ,  H01L21/76802 ,  H01L21/76819 ,  H01L21/76828 ,  H01L21/76895 ,  H01L21/823431 ,  H01L21/823475 ,  H01L23/481 ,  H01L23/5226 ,  H01L27/0886 ,  H01L29/41791 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/7851

Abstract: A method of forming a semiconductor device includes depositing a flowable dielectric layer on a substrate and annealing the flowable dielectric layer. The method further includes performing a high temperature (HT) doping process on the flowable dielectric layer. The FIT doping process may include implanting dopant ions into the flowable dielectric layer and heating the substrate during the implanting of the dopant ions. The heating of the substrate may include heating a substrate holder upon which the substrate is disposed and maintaining the substrate at a temperature above 100° C. An example benefit reduced the wet etch rate (WER) of the flowable dielectric layer.

公开(公告)号：US20170110550A1

公开(公告)日：2017-04-20

申请号：US15062062

申请日：2016-03-05

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chun-Hsiung TSAI ,  Kuo-Feng YU ,  Chien-Tai CHAN ,  Ziwei FANG ,  Kei-Wei CHEN ,  Huai-Tei YANG

IPC: H01L29/49 ,  H01L29/40 ,  H01L29/51 ,  H01L29/78 ,  H01L29/66

CPC classification number: H01L29/4966 ,  H01L21/2254 ,  H01L29/66492 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/7833 ,  H01L29/785

Abstract: A gate structure, a semiconductor device, and the method of forming a semiconductor device are provided. In various embodiments, the gate structure includes a gate stack and a doped spacer overlying a sidewall of the gate stack. The gate stack contains a doped work function metal (WFM) stack and a metal gate electrode overlying the doped WFM stack.

公开(公告)号：US20230238443A1

公开(公告)日：2023-07-27

申请号：US18129961

申请日：2023-04-03

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Cheng-Ming LIN ,  Sai-Hooi YEONG ,  Ziwei FANG ,  Chi On CHUI ,  Huang-Lin CHAO

IPC: H01L29/51 ,  H01L29/78 ,  H01L21/02 ,  H01L21/28 ,  H01L29/66 ,  H01L27/088

CPC classification number: H01L29/516 ,  H01L29/7851 ,  H01L21/02356 ,  H01L21/28176 ,  H01L29/66795 ,  H01L27/0886 ,  H01L29/6684 ,  H01L29/78391 ,  H01L29/785

Abstract: The present disclosure describes a device that is protected from the effects of an oxide on the metal gate layers of ferroelectric field effect transistors. In some embodiments, the device includes a substrate with fins thereon; an interfacial layer on the fins; a crystallized ferroelectric layer on the interfacial layer; and a metal gate layer on the ferroelectric layer,

公开(公告)号：US20210098457A1

公开(公告)日：2021-04-01

申请号：US16585267

申请日：2019-09-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chung-Liang CHENG ,  I-Ming CHANG ,  Ziwei FANG ,  Huang-Lin CHAO

IPC: H01L27/092 ,  H01L21/8238 ,  H01L21/02 ,  H01L29/66 ,  H01L29/78

Abstract: The present disclosure describes a semiconductor device that includes a semiconductor device that includes a first transistor having a first gate structure. The first gate structure includes a first gate dielectric layer doped with a first dopant at a first dopant concentration and a first work function layer on the first gate dielectric layer. The first gate structure also includes a first gate electrode on the first work function layer. The semiconductor device also includes a second transistor having a second gate structure, where the second gate structure includes a second gate dielectric layer doped with a second dopant at a second dopant concentration lower than the first dopant concentration. The second gate structure also includes a second work function layer on the second gate dielectric layer and a second gate electrode on the second work function layer.

公开(公告)号：US20210083068A1

公开(公告)日：2021-03-18

申请号：US16573498

申请日：2019-09-17

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Cheng-Ming LIN ,  Sai-Hooi YEONG ,  Ziwei FANG ,  Chi On CHUI ,  Huang-Lin CHAO

IPC: H01L29/51 ,  H01L29/78 ,  H01L29/66 ,  H01L21/28 ,  H01L21/02

Abstract: The present disclosure describes a method that can eliminate or minimize the formation of an oxide on the metal gate layers of ferroelectric field effect transistors. In some embodiments, the method includes providing a substrate with fins thereon; depositing an interfacial layer on the fins; depositing a ferroelectric layer on the interfacial layer; depositing a metal gate layer on the ferroelectric layer; exposing the metal gate layer to a metal-halide gas; and performing a post metallization annealing, where the exposing the metal gate layer to the metal-halide gas and the performing the post metallization annealing occur without a vacuum break.

公开(公告)号：US20210057550A1

公开(公告)日：2021-02-25

申请号：US16548446

申请日：2019-08-22

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chung-Liang CHENG ,  I-Ming CHANG ,  Hsiang-Pi CHANG ,  Hsueh-Wen TSAU ,  Ziwei FANG ,  Huang-Lin CHAO

IPC: H01L29/66 ,  H01L29/78

Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a semiconductor layer on a semiconductor substrate, forming an interfacial layer on the semiconductor layer, forming a first gate dielectric layer on the interfacial layer, introducing fluorine on the first gate dielectric layer, annealing the first gate dielectric layer, forming a second gate dielectric layer on the first gate dielectric layer, introducing fluorine on the second gate dielectric layer, annealing the second gate dielectric layer, and forming a gate stack structure on the second gate dielectric layer.

公开(公告)号：US20200335346A1

公开(公告)日：2020-10-22

申请号：US16386519

申请日：2019-04-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Christine Y OUYANG ,  Ziwei FANG

IPC: H01L21/28 ,  H01L29/66 ,  H01L29/423 ,  H01L29/78

Abstract: Structures and formation methods of a semiconductor device structure are provided. The method includes forming a dummy gate stack over a semiconductor substrate and forming a spacer element over a sidewall of the dummy gate stack. The method also includes removing the dummy gate stack to form a recess exposing a semiconductor strip and forming an inhibition layer over an interior surface of the spacer element. The method further includes forming a gate dielectric layer in the recess to selectively cover the semiconductor strip. The inhibition layer substantially prevents the gate dielectric layer from being formed on the inhibition layer. In addition, the method includes forming a metal gate electrode over the gate dielectric layer.

公开(公告)号：US20200328213A1

公开(公告)日：2020-10-15

申请号：US16911672

申请日：2020-06-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chung-Liang CHENG ,  Ziwei FANG

IPC: H01L27/092 ,  H01L21/8238 ,  H01L21/28 ,  H01L29/66 ,  H01L21/308 ,  H01L29/78 ,  H01L29/49 ,  H01L21/02

Abstract: A semiconductor device is provided. The semiconductor device includes first nanostructures vertically stacked over a first region of a substrate, a gate dielectric layer wrapping around the first nanostructures, a first oxygen blocking layer wrapping around the gate dielectric layer in the first region, a first-type work function layer wrapping around the first oxygen blocking layer in the first region, a second oxygen blocking layer wrapping around the first-type work function layer in the first region, and a second-type work function layer wrapping around the second oxygen blocking layer in the first region.

公开(公告)号：US20200273985A1

公开(公告)日：2020-08-27

申请号：US16285595

申请日：2019-02-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chung-Liang CHENG ,  Ziwei FANG

IPC: H01L29/78 ,  H01L21/02 ,  H01L21/762

Abstract: A method for forming a semiconductor device structure is provided. The method includes providing a substrate and an insulating layer over the substrate. The insulating layer has a trench partially exposing the substrate. The method includes forming a gate dielectric layer over an inner wall and a bottom of the trench. The method includes forming a mask layer over the gate dielectric layer over the bottom. The method includes removing the gate dielectric layer over the inner wall. The method includes removing the mask layer. The method includes forming a gate electrode in the trench.

公开(公告)号：US20200152746A1

公开(公告)日：2020-05-14

申请号：US16277262

申请日：2019-02-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsueh-Wen TSAU ,  Chun-I WU ,  Ziwei FANG ,  Huang-Lin CHAO ,  I-Ming CHANG ,  Chung-Liang CHENG ,  Chih-Cheng LIN

IPC: H01L29/40 ,  H01L29/66 ,  H01L29/78 ,  H01L29/423 ,  H01L29/49 ,  H01L21/28 ,  H01L21/768 ,  H01L23/532

Abstract: A method for forming a semiconductor device structure is provided. The method includes providing a substrate and an insulating layer over the substrate. The insulating layer has a trench partially exposing the substrate. The method includes forming a gate dielectric layer in the trench. The method includes forming a first metal-containing layer over the gate dielectric layer. The method includes forming a silicon-containing layer over the first metal-containing layer. The method includes forming a second metal-containing layer over the silicon-containing layer. The method includes forming a gate electrode layer in the trench and over the second metal-containing layer.