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公开(公告)号:US07053475B2
公开(公告)日:2006-05-30
申请号:US09754323
申请日:2001-01-05
申请人: Masatoshi Akagawa
发明人: Masatoshi Akagawa
IPC分类号: H01L21/44
CPC分类号: H01L25/0657 , H01L24/97 , H01L25/50 , H01L2224/16225 , H01L2224/32145 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/73204 , H01L2224/97 , H01L2225/06524 , H01L2225/06586 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01029 , H01L2924/01033 , H01L2924/01078 , H01L2924/12042 , H01L2924/15311 , H01L2924/00014 , H01L2224/81 , H01L2924/00012 , H01L2224/83 , H01L2924/00
摘要: An object of the present invention is to make it possible to effect a reliable and compact configuration for a semiconductor device when mounting a plurality of semiconductor elements in a single package, and achieve higher integration and higher functionality more effectively. In a multi-layer wiring board 20 in which wiring patterns (conductor layers) 22, 24, and 26, and insulating layers 23, 25, and 27, are formed alternately in multiple layers on a base substrate, and electrically connections are made between the wiring patterns through via holes VH1 and VH2, semiconductor elements 30 are imbedded and mounted inside the insulating layers 23, 25, and 27, and the semiconductor elements 30 are deployed so that they are electrically connected to wiring patterns that are covered by the insulating layers, and so that they are stacked up in a direction perpendicular to the planar dimension of the multi-layer wiring board 20.
摘要翻译: 本发明的一个目的是使得可以在将多个半导体元件安装在单个封装中时实现用于半导体器件的可靠且紧凑的配置,并且更有效地实现更高的集成度和更高的功能。 在布线图案(导体层)22,24,26以及绝缘层23,25,27在基底基板上交替形成多层的多层布线基板20中, 通过通孔VH 1和VH 2的布线图案,半导体元件30嵌入并安装在绝缘层23,25和27内部,并且半导体元件30被布置成使得它们电连接到被覆盖的布线图案 绝缘层,并且使它们在垂直于多层布线板20的平面尺寸的方向上堆叠。
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公开(公告)号:US20050094120A1
公开(公告)日:2005-05-05
申请号:US10974327
申请日:2004-10-27
IPC分类号: G03F7/20 , G03B27/54 , H01L21/027 , H05K3/00
CPC分类号: G03F7/70283 , G03F7/70291 , H05K3/0002 , H05K3/0005 , H05K3/0082
摘要: A direct exposure system comprises: a data mask that is a data object including drawing data; and a control mask that is a data object including at least one logical layer in which information about exposure conditions applied according to regions on a substrate is specified, and performs a direct exposure process using integrated data generated by combining the data mask with the control mask.
摘要翻译: 直接曝光系统包括:作为包括绘图数据的数据对象的数据掩模; 以及作为包括至少一个逻辑层的控制掩模,所述至少一个逻辑层指定了根据基板上的区域应用的关于曝光条件的信息,并且使用通过将数据掩模与控制掩模组合而生成的积分数据进行直接曝光处理 。
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公开(公告)号:US06380614B1
公开(公告)日:2002-04-30
申请号:US09602073
申请日:2000-06-23
申请人: Tsutomu Higuchi , Tomoharu Fujii , Shigeru Okamura , Tsuyoshi Sato , Takayoshi Wakabayashi , Masatoshi Akagawa
发明人: Tsutomu Higuchi , Tomoharu Fujii , Shigeru Okamura , Tsuyoshi Sato , Takayoshi Wakabayashi , Masatoshi Akagawa
IPC分类号: H01L2302
CPC分类号: G06K19/0775 , G06K19/07749 , H01L2224/05571 , H01L2224/05573 , H01L2224/05644 , H01L2224/16225 , H01L2224/16227 , H01L2224/81395 , H01L2924/00014
摘要: An IC card comprises: a plane coil having respective terminal sections; a semiconductor element arranged at a position not overlapping with the plane coil, the semiconductor element having electrode terminals; means for electrically connecting the respective terminal sections of the plane coil to the electrode terminals of the semiconductor element; and a reinforcing frame arranged on a face substantially the same as that of the semiconductor element so that the semiconductor element is surrounded by the reinforcing frame.
摘要翻译: IC卡包括:具有相应端子部分的平面线圈; 半导体元件,其布置在与所述平面线圈不重叠的位置处,所述半导体元件具有电极端子; 用于将平面线圈的各个端子部分电连接到半导体元件的电极端子的装置; 以及加强框架,其设置在与半导体元件基本相同的面上,使得半导体元件被加强框架包围。
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公开(公告)号:US6121688A
公开(公告)日:2000-09-19
申请号:US168148
申请日:1998-10-08
申请人: Masatoshi Akagawa
发明人: Masatoshi Akagawa
IPC分类号: H01L21/60 , H01L23/498 , H01L23/532 , H05K1/03 , H05K3/32 , H05K3/40 , H05K3/46 , H01L23/48
CPC分类号: H01L24/31 , H01L23/49816 , H01L23/49827 , H01L23/5328 , H01L24/28 , H01L24/83 , H05K3/4617 , H01L2224/13016 , H01L2224/13022 , H01L2224/13111 , H01L2224/29111 , H01L2224/2919 , H01L2224/2929 , H01L2224/293 , H01L2224/29339 , H01L2224/29355 , H01L2224/81903 , H01L2224/8319 , H01L2224/838 , H01L2224/83851 , H01L24/12 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01046 , H01L2924/01047 , H01L2924/0105 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/0132 , H01L2924/014 , H01L2924/0665 , H01L2924/0781 , H01L2924/14 , H01L2924/1517 , H01L2924/1579 , H01L2924/19041 , H01L2924/19043 , H05K1/0373 , H05K2201/0215 , H05K3/323 , H05K3/4084 , H05K3/4647
摘要: An anisotropic conductive sheet material includes a resin and conductive fillers, such as metallic particles, added in the resin. A conductive layer is formed on one of the surfaces of the anisotropic conductive sheet material. A circuit board includes a substrate having first and second surfaces and a circuit pattern being formed on the first surface of the substrate, an anisotropic conductive sheet having first and second surfaces, a circuit pattern being formed on the first surface thereof. The second surface of the anisotropic conductive sheet is adhered to the first surface of the substrate in such a manner that the circuit patterns are electrically connected to each other by means of the anisotropic conductive sheet. An electrically insulative layer formed on the first surface of the anisotropic conductive sheet to cover the circuit pattern thereof, except that external connecting portions thereof are exposed.
摘要翻译: 各向异性导电片材料包括树脂和添加在树脂中的诸如金属颗粒的导电填料。 在各向异性导电片材的一个表面上形成导电层。 电路板包括具有第一表面和第二表面的基板和形成在基板的第一表面上的电路图案,具有第一和第二表面的各向异性导电片,在其第一表面上形成电路图案。 各向异性导电片的第二表面以通过各向异性导电片彼此电连接的方式粘附到基板的第一表面。 形成在各向异性导电片的第一表面上以覆盖其电路图案的电绝缘层,除了外露连接部分外。
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