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    Method of making chip type solid electrolytic capacitor having a small size and a simple structure
    31.
    发明授权
    Method of making chip type solid electrolytic capacitor having a small size and a simple structure 有权
    制造尺寸小，结构简单的片式固体电解电容器的方法

    公开(公告)号：US07337513B2

    公开(公告)日：2008-03-04

    申请号：US11492541

    申请日：2006-07-25

    Applicant: Mitsunori Sano ,  Takashi Kono ,  Makoto Tsutsui

    Inventor： Mitsunori Sano ,  Takashi Kono ,  Makoto Tsutsui

    IPC: H01G7/00

    CPC classification number: H01G9/012 ,  H01G9/042 ,  H01G9/10 ,  H01L2924/0002 ,  Y10S257/924 ,  Y10T29/417 ,  Y10T29/435 ,  Y10T29/4913 ,  H01L2924/00

    Abstract: In a chip type solid electrolytic capacitor including a capacitor element and a packaging resin covering the capacitor element, the packaging resin has a mount surface and a side surface adjacent to the mount surface. A terminal is electrically connected to the capacitor element and coupled to the packaging resin. The terminal extends along the mount surface and the side surface to have an outer surface exposed from the packaging resin and to have an inner surface opposite to the outer terminal surface. The inner surface has a stepwise shape formed by forging.

    Abstract translation: 在包括电容器元件和覆盖电容器元件的封装树脂的芯片型固体电解电容器中，封装树脂具有与安装表面相邻的安装表面和侧表面。 端子电连接到电容器元件并且耦合到封装树脂。 端子沿着安装表面和侧表面延伸以具有从包装树脂露出的外表面并且具有与外端子表面相对的内表面。 内表面具有通过锻造形成的阶梯形状。

    Semiconductor memory device capable of operating at high speed and with low power consumption while ensuring reliability of memory cell
    33.
    发明申请
    Semiconductor memory device capable of operating at high speed and with low power consumption while ensuring reliability of memory cell 失效
    半导体存储器件能够在确保存储单元的可靠性的同时以高速和低功耗运行

    公开(公告)号：US20050169087A1

    公开(公告)日：2005-08-04

    申请号：US11030185

    申请日：2005-01-07

    Applicant: Takashi Kono ,  Hironori Iga

    Inventor： Takashi Kono ,  Hironori Iga

    IPC: G11C11/407 ,  G11C5/00 ,  G11C5/14 ,  G11C7/06 ,  G11C11/34 ,  G11C11/4074 ,  G11C29/02

    CPC classification number: G11C29/021 ,  G11C5/147 ,  G11C11/401 ,  G11C11/4074 ,  G11C29/02 ,  G11C29/028 ,  G11C2029/5004 ,  G11C2207/2227

    Abstract: A monitor circuit for monitoring external potential EXTVDD and variable delay circuit determine the time interval in which signal ZODACT is being at the L level according to the potential level of external potential EXTVDD, and thus the supplying time of external potential EXTVDD can be dynamically changed. When external potential EXTVDD is at the upper limit of specification of product, the supplying time is short, thereby preventing overcharge of memory cells or bit lines. When external potential EXTVDD is at the lower limit of specification of product, the supplying time becomes longer, thereby ensuring a sufficient over-driving time interval. It is possible to ensure the reliability of the memory cells and perform the reading operation throughout the entire range of the specification of product of external potential EXTVDD. Therefore, it is possible to provide a semiconductor memory device capable of performing a reading operation at high speeds while ensuring the reliability.

    Abstract translation: 用于监视外部电位EXTVDD和可变延迟电路的监视电路根据外部电位EXTVDD的电位电平确定信号ZODACT处于L电平的时间间隔，从而可以动态地改变外部电位EXTVDD的供电时间。 当外部电位EXTVDD处于产品规格的上限时，供电时间短，从而防止存储单元或位线的过充电。 当外部电位EXTVDD处于产品规格的下限时，供电时间变长，从而确保足够的过驱动时间间隔。 可以确保存储单元的可靠性，并在外部电位EXTVDD的产品规格的整个范围内执行读取操作。 因此，可以提供能够在确保可靠性的同时高速执行读取操作的半导体存储器件。

    Semiconductor memory device with structure of converting parallel data into serial data
    35.
    发明授权
    Semiconductor memory device with structure of converting parallel data into serial data 有权
    具有将并行数据转换为串行数据的结构的半导体存储器件

    公开(公告)号：US06914828B2

    公开(公告)日：2005-07-05

    申请号：US10440188

    申请日：2003-05-19

    Applicant: Takashi Kono

    Inventor： Takashi Kono

    IPC: G11C11/407 ,  G11C7/10 ,  G11C11/34 ,  G11C11/40 ,  G11C11/408 ,  G11C11/409 ,  G11C19/00 ,  H01L27/148

    CPC classification number: G11C7/1051 ,  G11C7/103 ,  G11C7/1036 ,  G11C19/00 ,  G11C2207/107

    Abstract: An amplifier circuit (R/A) conducts the first stage of ordering of whether to output data of four data bus pairs at the first half (first or second) or at the last half (third or fourth) based on the value of a signal EZORG1 reflecting the value of the least significant second bit of an externally applied column address. A switch circuit conducts the second stage of ordering to determine which is to be the first and the second of the two data output as the first half and to determine which is to be the third and the fourth of the two data output as the last half based on the value of a signal EZORG0 reflecting the value of the least significant bit in the externally applied column address.

    Abstract translation: 放大器电路（R / A）根据信号的值进行在前半（第一或第二）或后半（第三或第四）输出四个数据总线对的数据的排序的第一阶段 EZORG 1反映外部应用列地址的最低有效第二位的值。 开关电路进行第二阶段的排序，以确定作为上半部分输出的两个数据中的第一个和第二个是哪一个，并确定哪个是作为后半部分的两个数据输出中的第三个和第四个 基于反映外部施加的列地址中的最低有效位的值的信号EZORG 0的值。

    Semiconductor memory device allowing accurate burn-in test
    36.
    发明申请
    Semiconductor memory device allowing accurate burn-in test 失效
    半导体存储器件允许准确的老化测试

    公开(公告)号：US20050068838A1

    公开(公告)日：2005-03-31

    申请号：US10947213

    申请日：2004-09-23

    Applicant: Takashi Kono ,  Takeshi Hamamoto

    Inventor： Takashi Kono ,  Takeshi Hamamoto

    IPC: H01L27/108 ,  G11C8/08 ,  G11C11/34 ,  G11C11/401 ,  G11C11/409 ,  G11C29/12 ,  H01L21/8242 ,  H01L27/10 ,  G11C8/00

    CPC classification number: G11C8/08 ,  G11C11/401 ,  G11C29/12 ,  G11C2029/1202

    Abstract: An insulated gate type field effect transistor in a memory cell array is a transistor having a gate insulating film which is thicker than a gate insulating film of an insulated gate type field effect transistor in an array peripheral circuit. DRAM (Dynamic Random Access Memory) cell-based semiconductor memory device can be implemented which allows a burn-in test to be accurately performed without degrading sensing operation characteristics even under a low power supply voltage.

    Abstract translation: 存储单元阵列中的绝缘栅型场效应晶体管是具有比阵列外围电路中的绝缘栅型场效应晶体管的栅极绝缘膜厚的栅极绝缘膜的晶体管。 可以实现DRAM（动态随机存取存储器）基于单元的半导体存储器件，其即使在低电源电压下也能够精确地执行老化测试而不降低感测操作特性。

    Semiconductor device capable of reducing noise to signal line
    37.
    发明授权
    Semiconductor device capable of reducing noise to signal line 失效
    能够将噪声降低到信号线的半导体器件

    公开(公告)号：US06744273B2

    公开(公告)日：2004-06-01

    申请号：US10127763

    申请日：2002-04-23

    Applicant: Makoto Kitagawa ,  Takashi Kono

    Inventor： Makoto Kitagawa ,  Takashi Kono

    IPC: H03K1762

    CPC classification number: G11C7/02 ,  G11C5/063 ,  G11C7/12 ,  G11C11/4094

    Abstract: A semiconductor device includes a signal line and two adjacent wirings formed on a first substrate layer, an adjacent wiring formed on a second substrate layer, and an adjacent wiring formed on a third substrate layer. A logical level on the signal line is set constant, a first line capacitance is formed between the signal line and one of the adjacent wirings on the first substrate layer, and a second line capacitance is formed between the signal line and the other of adjacent wirings on the first substrate layer. Also, a signal is supplied to the adjacent wiring on the second substrate layer and the adjacent wiring on the third substrate layer. As a result, noise from the other adjacent wirings to the signal line can be reduced.

    Abstract translation: 半导体器件包括信号线和形成在第一衬底层上的两个相邻布线，形成在第二衬底层上的相邻布线和形成在第三衬底层上的相邻布线。 信号线上的逻辑电平被设定为恒定，在信号线和第一衬底层上的相邻布线中的一个之间形成第一线电容，并且在信号线和相邻布线中的另一条之间形成第二线电容 在第一基底层上。 此外，信号被提供给第二基板层上的相邻布线和第三基板层上的相邻布线。 结果，可以减少来自信号线的其他相邻布线的噪声。

    Semiconductor memory device capable of switching reference voltage for generating intermediate voltage
    38.
    发明授权
    Semiconductor memory device capable of switching reference voltage for generating intermediate voltage 失效
    能够切换用于产生中间电压的基准电压的半导体存储器件

    公开(公告)号：US06449208B1

    公开(公告)日：2002-09-10

    申请号：US09923454

    申请日：2001-08-08

    Applicant: Takashi Kono ,  Yuichiro Komiya

    Inventor： Takashi Kono ,  Yuichiro Komiya

    IPC: G11C700

    CPC classification number: G11C29/12 ,  G11C5/147

    Abstract: A semiconductor memory device has a half Vdds generating circuit. The half Vdds generating circuit includes reference voltage generating circuits, a selecting circuit, and a driver circuit. In a normal mode, the driver circuit receives voltages Vnd1 and Vpd1 obtained by dividing an array operation voltage Vdds from the reference voltage generating circuit and outputs a precharge voltage Vb1 from an output node. In a test mode, the driver circuit receives voltages Vnd2 and Vpd2 obtained by dividing the voltage Vddp from the reference-voltage generating circuit, and outputs a precharge voltage Vb1 from the output node. As a result, a voltage as a reference used to generate an intermediate voltage can be switched between the normal mode and the test mode.

    Abstract translation: 半导体存储器件具有半Vdds发生电路。 半Vdds发生电路包括参考电压发生电路，选择电路和驱动器电路。 在正常模式下，驱动电路接收通过从参考电压产生电路中分离阵列工作电压Vdds获得的电压Vnd1和Vpd1，并从输出节点输出预充电电压Vb1。 在测试模式中，驱动电路接收通过对来自基准电压产生电路的电压Vddp进行分压而获得的电压Vnd2和Vpd2，并从输出节点输出预充电电压Vb1。 结果，可以在正常模式和测试模式之间切换用于产生中间电压的用作基准的电压。

    Dynamic semiconductor memory device with reduced current consumption in sensing operation
    39.
    发明授权
    Dynamic semiconductor memory device with reduced current consumption in sensing operation 有权
    动态半导体存储器件，在感测操作中具有降低的电流消耗

    公开(公告)号：US06337824B1

    公开(公告)日：2002-01-08

    申请号：US09455541

    申请日：1999-12-07

    Applicant: Takashi Kono ,  Takeshi Hamamoto

    Inventor： Takashi Kono ,  Takeshi Hamamoto

    IPC: G11C702

    CPC classification number: H01L27/10897 ,  G11C11/406 ,  G11C11/4074 ,  G11C11/4091

    Abstract: A decoupling capacitor is coupled to a sense power supply line with respect to a sense amplifier circuit group, and the sense power supply line is selectively coupled with a power supply node in response to an operation mode of a sense amplifier. In a sensing operation, the potential of a bit line is determined by redistribution of charges between the decoupling capacitor and a load capacitor of the bit line. Refresh characteristics is improved without increasing a sense current and showing down the sensing operation.

    Abstract translation: 解耦电容器相对于读出放大器电路组耦合到感测电源线，并且响应于读出放大器的操作模式，感测电源线选择性地与电源节点耦合。 在感测操作中，位线的电位通过去耦电容器和位线的负载电容器之间的电荷的再分配来确定。 在不增加感测电流并显示感测操作的情况下，刷新特性得到改善。

    Semiconductor device capable of stably generating internal voltage with low supply voltage
    40.
    发明授权
    Semiconductor device capable of stably generating internal voltage with low supply voltage 失效
    能够以低电源电压稳定地产生内部电压的半导体装置

    公开(公告)号：US06333670B1

    公开(公告)日：2001-12-25

    申请号：US09456521

    申请日：1999-12-08

    Applicant: Takashi Kono ,  Takeshi Hamamoto

    Inventor： Takashi Kono ,  Takeshi Hamamoto

    IPC: G05F110

    CPC classification number: G05F1/465

    Abstract: Change in internal voltage on an internal voltage line is detected as discharging current of a capacitance element via an MOS transistor to change a charged voltage of the capacitance element. According to the charged voltage of the capacitance element, a current drive transistor is driven to supply a current to the internal voltage line. The internal voltage is stably generated with low current consumption and small occupation area.

    Abstract translation: 内部电压线的内部电压的变化通过MOS晶体管被检测为电容元件的放电电流，以改变电容元件的充电电压。 根据电容元件的充电电压，驱动电流驱动晶体管以向内部电压线提供电流。 内部电压稳定产生，电流消耗小，占用面积小。

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