公开(公告)号：US06781172B2

公开(公告)日：2004-08-24

申请号：US09800493

申请日：2001-03-08

申请人： Hiroshi Moriya ,  Tomio Iwasaki ,  Hiroyuki Ohta ,  Shinpei Iijima ,  Isamu Asano ,  Yuzuru Ohji ,  Yoshitaka Nakamura

发明人： Hiroshi Moriya ,  Tomio Iwasaki ,  Hiroyuki Ohta ,  Shinpei Iijima ,  Isamu Asano ,  Yuzuru Ohji ,  Yoshitaka Nakamura

IPC分类号： H01L2976

CPC分类号： H01L28/60 ,  H01L27/10814 ,  H01L28/55

摘要： A semiconductor device equipped with information storage capacitor comprising a first capacitor electrode, an oxide film, a second capacitor electrode and insulating films containing silicon as a main constituting element, wherein at least one of first and second capacitor electrodes contains as a main constituting element at least one element selected from rhodium, ruthenium, iridium, osmium and platinum, and as an adding element at least one element selected from palladium, nickel, cobalt and titanium, is excellent in adhesiveness between the capacitor electrodes and the insulating films.

摘要翻译： 一种配备有信息存储电容器的半导体器件，包括第一电容器电极，氧化物膜，第二电容器电极和以硅为主要构成元素的绝缘膜，其中，第一和第二电容器电极中的至少一个包含作为主要构成元素 选自铑，钌，铱，锇和铂中的至少一种元素，并且作为添加元素，选自钯，镍，钴和钛中的至少一种元素，电容器电极和绝缘膜之间的粘附性优异。

公开(公告)号：US20050269662A1

公开(公告)日：2005-12-08

申请号：US11139002

申请日：2005-05-25

申请人： Norio Ishitsuka ,  Jun Tanaka ,  Tomio Iwasaki ,  Hiroyuki Ohta

发明人： Norio Ishitsuka ,  Jun Tanaka ,  Tomio Iwasaki ,  Hiroyuki Ohta

IPC分类号： H01L21/76 ,  H01L21/312 ,  H01L21/316 ,  H01L21/8234 ,  H01L21/8247 ,  H01L27/08 ,  H01L27/115 ,  H01L29/78 ,  H01L29/788 ,  H01L29/792

CPC分类号： H01L21/823481 ,  H01L21/02134 ,  H01L21/02137 ,  H01L21/02203 ,  H01L21/3124 ,  H01L21/31662 ,  H01L29/7833

摘要： To suppress occurrence of dislocation in a substrate of a semiconductor device at an end portion of a gate electrode. Provided is a semiconductor device having a plurality of element formation regions formed over the main surface of a semiconductor substrate, an element isolation trench located between the element formation regions and having an element isolation insulating film embedded therein, and a gate insulating film, a gate electrode and a plurality of interconnect layers formed thereabove, each formed in the element formation region, wherein the element isolation trench has a thermal oxide film formed between the semiconductor substrate and the element isolation insulating film, and the element isolation film has a great number of micro-pores formed inside thereof and is more porous than the thermal oxide film.

摘要翻译： 为了抑制在栅电极的端部处的半导体器件的衬底中的位错的发生。 提供了一种半导体器件，其具有形成在半导体衬底的主表面上的多个元件形成区域，位于元件形成区域之间并且具有嵌入元件隔离绝缘膜的元件隔离沟槽，以及栅极绝缘膜，栅极 电极和形成在其上的多个互连层，各自形成在元件形成区域中，其中元件隔离沟槽具有形成在半导体衬底和元件隔离绝缘膜之间的热氧化膜，并且元件隔离膜具有大量 在其内形成的微孔比热氧化膜多孔。

公开(公告)号：US06927439B2

公开(公告)日：2005-08-09

申请号：US10923002

申请日：2004-08-23

申请人： Hiroshi Moriya ,  Tomio Iwasaki ,  Hiroyuki Ohta ,  Shinpei Iijima ,  Isamu Asano ,  Yuzuru Ohji ,  Yoshitaka Nakamura

发明人： Hiroshi Moriya ,  Tomio Iwasaki ,  Hiroyuki Ohta ,  Shinpei Iijima ,  Isamu Asano ,  Yuzuru Ohji ,  Yoshitaka Nakamura

IPC分类号： H01L27/10 ,  H01L21/02 ,  H01L21/8242 ,  H01L27/108 ,  H01L29/76

CPC分类号： H01L28/60 ,  H01L27/10814 ,  H01L28/55

摘要： A semiconductor device equipped with information storage capacitor comprising a first capacitor electrode, an oxide film, a second capacitor electrode and insulating films containing silicon as a main constituting element, wherein at least one of first and second capacitor electrodes contains as a main constituting element at least one element selected from rhodium, ruthenium, iridium, osmium and platinum, and as an adding element at least one element selected from palladium, nickel, cobalt and titanium, is excellent in adhesiveness between the capacitor electrodes and the insulating films.

摘要翻译： 一种配备有信息存储电容器的半导体器件，包括第一电容器电极，氧化物膜，第二电容器电极和以硅为主要构成元素的绝缘膜，其中，第一和第二电容器电极中的至少一个包含作为主要构成元素 选自铑，钌，铱，锇和铂中的至少一种元素，并且作为添加元素，选自钯，镍，钴和钛中的至少一种元素，电容器电极和绝缘膜之间的粘附性优异。

公开(公告)号：US06566149B1

公开(公告)日：2003-05-20

申请号：US09787250

申请日：2001-03-16

申请人： Masatoshi Kanamaru ,  Atsushi Hosogane ,  Yoshihige Endou ,  Ryuji Kouno ,  Hideo Miura ,  Shinji Tanaka ,  Hiroyuki Ohta ,  Akihiko Ariga ,  Naoto Ban ,  Hideyuki Aoki

发明人： Masatoshi Kanamaru ,  Atsushi Hosogane ,  Yoshihige Endou ,  Ryuji Kouno ,  Hideo Miura ,  Shinji Tanaka ,  Hiroyuki Ohta ,  Akihiko Ariga ,  Naoto Ban ,  Hideyuki Aoki

IPC分类号： G01R3126

CPC分类号： G01R3/00

摘要： For an inspection tray, a silicon substrate including a beam or a diaphragm, a probe and wiring is used. To highly accurately position a chip to be inspected, a second substrate for alignment is disposed on the substrate. To position the probe having wiring disposed on the first substrate and the electrode pad of the chip to be inspected, a projection or a groove is formed in each of both substrates. Preferably, the projection or groove should be formed by silicon anisotorpic etching to have a (111) crystal surface. As another machining method, dry etching can be used for machining the positioning projection or groove. By using an inductively coupled plasma-reactive ion etching (ICP-RIE) device for the dry etching, a vertical column or groove can be easily machined.

摘要翻译： 对于检查托盘，使用包括梁或隔膜，探针和布线的硅基板。 为了高精度地定位待检查的芯片，在基板上设置用于对准的第二基板。 为了定位具有设置在第一基板上的布线的探针和要检查的芯片的电极焊盘，在两个基板中的每一个中形成突起或凹槽。 优选地，突起或凹槽应由硅各向异性蚀刻形成以具有（111）晶体表面。 作为另一种加工方法，可以使用干蚀刻来加工定位突起或凹槽。 通过使用用于干蚀刻的电感耦合等离子体反应离子蚀刻（ICP-RIE）装置，可以容易地加工垂直的柱或槽。

公开(公告)号：US06544884B2

公开(公告)日：2003-04-08

申请号：US10022525

申请日：2001-12-20

申请人： Hiroyuki Ohta ,  Hideo Miura ,  Kazushige Sato ,  Takeshi Kimura ,  Hiyoo Masuda

发明人： Hiroyuki Ohta ,  Hideo Miura ,  Kazushige Sato ,  Takeshi Kimura ,  Hiyoo Masuda

IPC分类号： H01L214763

CPC分类号： H01L23/5283 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device capable of operating at a high speed or of having many functions. In this device, delamination of buried electrodes is prevented and thus high reliability is offered. The depth A of contact holes, the minimum linewidth R of a lower metallization layer, and the thickness B of the lower metallization layer satisfy relations given by (0.605/R)0.5

公开(公告)号：US06337517B1

公开(公告)日：2002-01-08

申请号：US09151590

申请日：1998-09-11

申请人： Hiroyuki Ohta ,  Hideo Miura ,  Kazushige Sato ,  Takeshi Kimura ,  Hiroo Masuda

发明人： Hiroyuki Ohta ,  Hideo Miura ,  Kazushige Sato ,  Takeshi Kimura ,  Hiroo Masuda

IPC分类号： H01L2348

CPC分类号： H01L23/5283 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device capable of operating at a high speed or of having many functions. In this device, delamination of buried electrodes is prevented and thus high reliability is offered. The depth A of contact holes, the minimum linewidth R of a lower metallization layer, and the thickness B of the lower metallization layer satisfy relations given by (0.605/R)0.5

摘要翻译： 能够高速运转或具有许多功能的半导体装置。 在该装置中，防止了埋入电极的分层，从而提供了高可靠性。 接触孔的深度A，下部金属化层的最小线宽R和下部金属化层的厚度B满足关系式

公开(公告)号：US07244643B2

公开(公告)日：2007-07-17

申请号：US10496766

申请日：2002-11-21

申请人： Norio Ishitsuka ,  Yukihiro Kumagai ,  Hideo Miura ,  Shuji Ikeda ,  Toshifumi Takeda ,  Hiroyuki Ohta

发明人： Norio Ishitsuka ,  Yukihiro Kumagai ,  Hideo Miura ,  Shuji Ikeda ,  Toshifumi Takeda ,  Hiroyuki Ohta

IPC分类号： H01L21/8238

CPC分类号： H01L29/7846 ,  H01L21/76224 ,  H01L21/823807 ,  H01L21/823878 ,  H01L29/7842

摘要： The object of the present invention is to provide a semiconductor device comprising an n-type channel field effect transistor and a p-type channel field effect transistor, which has a high degree of reliability and excellent drain current characteristics. The gist of the invention for attaining the object resides in disposing a silicon nitride film to the side wall of a trench for an active region in which the n-type channel field effect transistor is formed and disposing the silicon nitride film only in the direction perpendicular to the channel direction to the sidewall of the trench for the active region of the p-type channel field effect transistor. According to the present invention, a semiconductor device comprising an n-type channel field effect transistor and a p-type channel field effect transistor of excellent current characteristics can be provided.

摘要翻译： 本发明的目的是提供一种包括n型沟道场效应晶体管和p型沟道场效应晶体管的半导体器件，其具有高可靠性和优异的漏极电流特性。 实现本发明的要点在于，在形成有n型沟道场效应晶体管的有源区的沟槽的侧壁上设置氮化硅膜，仅在垂直方向上设置氮化硅膜 到通道方向，到p型沟道场效应晶体管的有源区的沟槽的侧壁。 根据本发明，可以提供包括n型沟道场效应晶体管和具有优异电流特性的p型沟道场效应晶体管的半导体器件。

公开(公告)号：US06982465B2

公开(公告)日：2006-01-03

申请号：US10433786

申请日：2001-12-06

申请人： Yukihiro Kumagai ,  Hiroyuki Ohta ,  Fumio Ootsuka ,  Shuji Ikeda ,  Takahiro Onai ,  Hideo Miura ,  Katsuhiko Ichinose ,  Toshifumi Takeda

发明人： Yukihiro Kumagai ,  Hiroyuki Ohta ,  Fumio Ootsuka ,  Shuji Ikeda ,  Takahiro Onai ,  Hideo Miura ,  Katsuhiko Ichinose ,  Toshifumi Takeda

IPC分类号： H01L29/76

CPC分类号： H01L29/7842 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823842 ,  H01L27/092

摘要： The present invention provides a semiconductor device including n-channel field effect transistors and p-channel field effect transistors all of which have excellent drain current characteristics.In a semiconductor device including an n-channel field effect transistor 10 and a p-channel field effect transistor 30, a stress control film 19 covering a gate electrode 15 of the n-channel field effect transistor 10 undergoes film stress mainly composed of tensile stress. A stress control film 39 covering a gate electrode 15 of the p-channel field effect transistor 30 undergoes film stress mainly caused by compression stress compared to the film 19 of the n-channel field effect transistor 10. Accordingly, drain current is expected to be improved in both the n-channel field effect transistor and the p-channel field effect transistor. Consequently, the characteristics can be generally improved.

摘要翻译： 本发明提供一种包括n沟道场效应晶体管和p沟道场效应晶体管的半导体器件，其全部具有优良的漏极电流特性。 在包括n沟道场效应晶体管10和p沟道场效应晶体管30的半导体器件中，覆盖n沟道场效应晶体管10的栅电极15的应力控制膜19经受主要由拉伸应力 。 与n沟道场效应晶体管10的膜19相比，覆盖p沟道场效应晶体管30的栅电极15的应力控制膜39主要由压缩应力引起的膜应力。 因此，预期在n沟道场效应晶体管和p沟道场效应晶体管两者中都会改善漏极电流。 因此，通常可以提高特性。

公开(公告)号：US20050121727A1

公开(公告)日：2005-06-09

申请号：US10496766

申请日：2002-11-11

申请人： Norio Ishitsuka ,  Yukihiro Kumagai ,  Hideo Miura ,  Shuji Ikeda ,  Toshifumi Takeda ,  Hiroyuki Ohta

发明人： Norio Ishitsuka ,  Yukihiro Kumagai ,  Hideo Miura ,  Shuji Ikeda ,  Toshifumi Takeda ,  Hiroyuki Ohta

IPC分类号： H01L21/76 ,  H01L21/762 ,  H01L21/822 ,  H01L21/8238 ,  H01L27/04 ,  H01L27/08 ,  H01L27/092 ,  H01L27/10 ,  H01L29/76 ,  H01L29/94 ,  H01L31/113

CPC分类号： H01L29/7846 ,  H01L21/76224 ,  H01L21/823807 ,  H01L21/823878 ,  H01L29/7842

摘要： The object of the present invention is to provide a semiconductor device comprising an n-type channel field effect transistor and a p-type channel field effect transistor, which has a high degree of reliability and excellent drain current characteristics. The gist of the invention for attaining the object resides in disposing a silicon nitride film to the side wall of a trench for an active region in which the n-type channel field effect transistor is formed and disposing the silicon nitride film only in the direction perpendicular to the channel direction to the sidewall of the trench for the active region of the p-type channel field effect transistor. According to the present invention, a semiconductor device comprising an n-type channel field effect transistor and a p-type channel field effect transistor of excellent current characteristics can be provided.

摘要翻译： 本发明的目的是提供一种包括n型沟道场效应晶体管和p型沟道场效应晶体管的半导体器件，其具有高可靠性和优异的漏极电流特性。 实现本发明的要点在于，在形成有n型沟道场效应晶体管的有源区的沟槽的侧壁上设置氮化硅膜，仅在垂直方向上设置氮化硅膜 到通道方向，到p型沟道场效应晶体管的有源区的沟槽的侧壁。 根据本发明，可以提供包括n型沟道场效应晶体管和具有优异电流特性的p型沟道场效应晶体管的半导体器件。

公开(公告)号：US06891761B2

公开(公告)日：2005-05-10

申请号：US10767053

申请日：2004-01-30

申请人： Yukihiro Kumagai ,  Hideo Miura ,  Hiroyuki Ohta ,  Michihiro Mishima ,  Katsuyuki Nakanishi

发明人： Yukihiro Kumagai ,  Hideo Miura ,  Hiroyuki Ohta ,  Michihiro Mishima ,  Katsuyuki Nakanishi

IPC分类号： H01L21/76 ,  H01L21/8234 ,  H01L21/8242 ,  H01L27/08 ,  H01L27/108 ,  G11C16/06

CPC分类号： H01L29/7842 ,  H01L21/823412 ,  H01L21/823481 ,  H01L27/10873 ,  H01L27/10897

摘要： A semiconductor device is provided including a circuit employing two or more field-effect transistor that are desired to have equal characteristics, capable of realizing high reliability and superior transistor characteristics. The transistors which are desired to have equal characteristics are placed in the semiconductor device so as to have the same STI trench width (the width of shallow trench isolation adjacent to an active area in which the transistor is formed). By such composition, stress growing in the active area due to the shallow trench isolation is equalized among the transistors, and, thereby, the characteristics of the transistors can be equalized.

摘要翻译： 提供一种半导体器件，其包括使用期望具有相同特性的两个或更多个场效应晶体管的电路，能够实现高可靠性和优异的晶体管特性。 期望具有相同特性的晶体管被​​放置在半导体器件中，以具有相同的STI沟槽宽度（与形成晶体管的有源区相邻的浅沟槽隔离的宽度）。 通过这样的组成，由于浅沟槽隔离而在有源区中生长的应力在晶体管之间被均衡，从而可以使晶体管的特性相等。