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    Methods that mitigate excessive source/drain silicidation in full gate silicidation metal gate flows
    31.
    发明申请
    Methods that mitigate excessive source/drain silicidation in full gate silicidation metal gate flows 审中-公开
    减少全栅极硅化金属栅流过多的源极/漏极硅化物的方法

    公开(公告)号：US20060258074A1

    公开(公告)日：2006-11-16

    申请号：US11127737

    申请日：2005-05-12

    Applicant: Mark Visokay ,  James Chambers ,  Luigi Colombo

    Inventor： Mark Visokay ,  James Chambers ,  Luigi Colombo

    IPC: H01L21/8238 ,  H01L21/4763

    CPC classification number: H01L21/28097 ,  H01L21/823814 ,  H01L21/823835 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833

    Abstract: The present invention facilitates semiconductor fabrication by providing methods of fabrication that form metal silicide gates and mitigate formation of silicide region defects near channel regions. A dielectric layer is formed over a semiconductor device (306). Polysilicon is deposited on the dielectric layer to form a gate electrode layer (308) and a patterning operation is then performed to form gate structures (310). Source/drain regions are formed (320) and the gate structures are tuned to obtain a selected work function (324). A metal is then selectively deposited on only the gate structures (328) and a thermal process is performed that reacts the deposited metal with polysilicon of the gate layer to obtain a metal suicide material (330).

    Abstract translation: 本发明通过提供形成金属硅化物栅极的制造方法和减少沟道区附近的硅化物区域缺陷的形成来促进半导体制造。 在半导体器件（306）上形成电介质层。 多晶硅沉积在电介质层上以形成栅极电极层（308），然后执行构图操作以形成栅极结构（310）。 源极/漏极区域形成（320）并且栅极结构被调谐以获得所选择的功函数（324）。 然后仅在栅极结构（328）上选择性地沉积金属，并且执行使沉积的金属与栅极层的多晶硅反应以获得金属硅化物材料（330）的热处理。

    Semiconductor CMOS devices and methods with NMOS high-k dielectric present in core region that mitigate damage to dielectric materials
    32.
    发明申请
    Semiconductor CMOS devices and methods with NMOS high-k dielectric present in core region that mitigate damage to dielectric materials 有权
    具有NMOS高k电介质的半导体CMOS器件和方法存在于芯区中，可减轻介电材料的损坏

    公开(公告)号：US20060246651A1

    公开(公告)日：2006-11-02

    申请号：US11118843

    申请日：2005-04-29

    Applicant: James Chambers ,  Mark Visokay ,  Luigi Colombo

    Inventor： James Chambers ,  Mark Visokay ,  Luigi Colombo

    IPC: H01L21/8238 ,  H01L21/8234

    CPC classification number: H01L21/823857 ,  H01L21/823842 ,  Y10S438/981

    Abstract: The present invention facilitates semiconductor fabrication by providing methods of fabrication that selectively form high-k dielectric layers within NMOS regions. An I/O dielectric layer is formed in core and I/O regions of a semiconductor device (506). The I/O dielectric layer is removed (508) from the core region of the device. A core dielectric layer is formed in the core region (510). A barrier layer is deposited and patterned to expose the NMOS devices of the core region (512). The core dielectric layer is removed from the core NMOS devices (514). A high-k dielectric layer is formed (514) over the core and I/O regions. Then, the high-k dielectric layer is removed (512) from PMOS regions/devices of the core region and the NMOS and PMOS regions/devices of the I/O region.

    Abstract translation: 本发明通过提供在NMOS区内选择性地形成高k电介质层的制造方法来促进半导体制造。 在半导体器件（506）的芯和I / O区域中形成I / O电介质层。 从器件的芯区域去除（508）I / O电介质层。 在芯区域（510）中形成芯介质层。 屏蔽层被沉积并图案化以暴露核心区域（512）的NMOS器件。 从核心NMOS器件（514）去除芯介质层。 在核心和I / O区域上形成高k电介质层（514）。 然后，从核心区域的PMOS区域/器件和I / O区域的NMOS和PMOS区域/器件去除高k电介质层（512）。

    Triple-gate MOSFET transistor and methods for fabricating the same
    33.
    发明申请
    Triple-gate MOSFET transistor and methods for fabricating the same 审中-公开
    三栅MOSFET晶体管及其制造方法

    公开(公告)号：US20050184319A1

    公开(公告)日：2005-08-25

    申请号：US11112463

    申请日：2005-04-21

    Applicant: James Chambers ,  Mark Visokay

    Inventor： James Chambers ,  Mark Visokay

    IPC: H01L21/00 ,  H01L21/336 ,  H01L29/76 ,  H01L29/78

    CPC classification number: H01L29/7833 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/66795

    Abstract: Transistors and fabrication methods are presented in which a semiconductor body is deposited in a cavity of a temporary form structure above a semiconductor starting structure. The formed semiconductor body can be epitaxial silicon deposited in the form cavity over a silicon substrate, and includes three body portions, two of which are doped to form source/drains, and the other forming a transistor channel that overlies the starting structure. A gate structure is formed along one or more sides of the channel body portion to create a MOS transistor.

    Abstract translation: 提出了晶体管和制造方法，其中半导体体沉积在半导体起始结构之上的临时形式结构的空腔中。 所形成的半导体本体可以是外延硅沉积在硅衬底上的空腔中，并且包括三个主体部分，其中两个被掺杂以形成源极/漏极，另一个形成覆盖起始结构的晶体管沟道。 栅极结构沿通道主体部分的一侧或多侧形成以形成MOS晶体管。

    Triple-gate mosfet transistor and methods for fabricating the same
    36.
    发明申请
    Triple-gate mosfet transistor and methods for fabricating the same 有权
    三栅MOSFET晶体管及其制造方法

    公开(公告)号：US20050095764A1

    公开(公告)日：2005-05-05

    申请号：US10696539

    申请日：2003-10-29

    Applicant: James Chambers ,  Mark Visokay

    Inventor： James Chambers ,  Mark Visokay

    IPC: H01L21/00 ,  H01L21/336 ,  H01L29/76 ,  H01L29/78

    CPC classification number: H01L29/7833 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/66795

    Abstract: Fabrication methods are presented in which a semiconductor body is deposited in a cavity of a temporary form structure above a semiconductor starting structure. The formed semiconductor body can be epitaxial silicon deposited in the form cavity over a silicon substrate, and includes three body portions, two of which are doped to form source/drains, and the other forming a transistor channel that overlies the starting structure. A gate structure is formed along one or more sides of the channel body portion to create a MOS transistor.

    Abstract translation: 提出了制造方法，其中将半导体体沉积在半导体起始结构之上的临时形式结构的空腔中。 所形成的半导体本体可以是外延硅沉积在硅衬底上的空腔中，并且包括三个主体部分，其中两个被掺杂以形成源极/漏极，另一个形成覆盖起始结构的晶体管沟道。 栅极结构沿通道主体部分的一侧或多侧形成以形成MOS晶体管。

    Reliable high voltage gate dielectric layers using a dual nitridation process
    40.
    发明申请
    Reliable high voltage gate dielectric layers using a dual nitridation process 有权
    使用双重氮化工艺的可靠的高压栅极电介质层

    公开(公告)号：US20070117331A1

    公开(公告)日：2007-05-24

    申请号：US11626624

    申请日：2007-01-24

    Applicant: Rajesh Khamankar ,  Douglas Grider ,  Hiroaki Niimi ,  April Gurba ,  Toan Tran ,  James Chambers

    Inventor： Rajesh Khamankar ,  Douglas Grider ,  Hiroaki Niimi ,  April Gurba ,  Toan Tran ,  James Chambers

    IPC: H01L21/336 ,  H01L29/76

    CPC classification number: H01L21/823462 ,  H01L21/28185 ,  H01L21/28202 ,  H01L21/3144 ,  H01L29/518

    Abstract: Dual gate dielectric layers are formed on a semiconductor substrate for MOS transistor fabrication. A first dielectric layer (30) is formed on a semiconductor substrate (10). A first plasma nitridation process is performed on said first dielectric layer. The first dielectric layer (30) is removed in regions of the substrate and a second dielectric layer (50) is formed in these regions. A second plasma nitridation process is performed on the first dielectric layer and the second dielectric. MOS transistors (160, 170) are then fabricated using the dielectric layers (30, 50).

    Abstract translation: 在用于MOS晶体管制造的半导体衬底上形成双栅介质层。 第一电介质层（30）形成在半导体衬底（10）上。 在所述第一介电层上进行第一等离子体氮化处理。 在衬底的区域中去除第一电介质层（30），并且在这些区域中形成第二电介质层（50）。 在第一电介质层和第二电介质上进行第二等离子体氮化处理。 然后使用电介质层（30,50）制造MOS晶体管（160,170）。

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