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31.发明授权Method for removing metal foot during high-k dielectric/metal gate etching 有权在高k电介质/金属栅极蚀刻期间去除金属脚的方法公开(公告)号：US07579282B2
公开(公告)日：2009-08-25
申请号：US11331786
申请日：2006-01-13
IPC分类号： H01L21/285 , H01L21/3065
CPC分类号： H01L21/02071 , H01L21/28088 , H01L21/32136 , H01L21/32137 , H01L21/32139 , H01L29/4966 , H01L29/517 , H01L29/518
摘要： A metal layer etch process deposits, patterns and anisotropically etches a polysilicon layer (24) down to an underlying metal layer (22) to form an etched polysilicon structure (54) with polymer layers (50, 52) formed on its sidewall surfaces. The polymer layer (50, 52) are removed to expose an additional surface area (60, 62) of the metal layer (22), and dielectric layers (80, 82) are formed on the sidewall surfaces of the etched polysilicon structure (54). Next, the metal layer (22) is plasma etched to form an etched metal layer (95) with substantially vertical sidewall surfaces (97, 99) by simultaneously charging the dielectric layers (80, 82) to change plasma ion trajectories near the dielectric layers (80, 82) so that plasma ions (92, 94) impact the sidewall surfaces (97, 99) in a more perpendicular angle to enhance etching of the sidewall surfaces (97, 99) of the etched metal layer (95).
摘要翻译： 金属层蚀刻工艺沉积，图案和各向异性地将多晶硅层（24）向下蚀刻到下面的金属层（22）以形成蚀刻的多晶硅结构（54），其上形成有在其侧壁表面上的聚合物层（50,52）。 去除聚合物层（50,52）以暴露金属层（22）的另外的表面区域（60,62），并且在蚀刻的多晶硅结构（54）的侧壁表面上形成介电层（80,82） ）。 接下来，通过同时对电介质层（80,82）充电以改变电介质层附近的等离子体离子轨迹，等离子体蚀刻金属层（22）以形成具有基本上垂直的侧壁表面（97,99）的蚀刻金属层（95） （80,82），使得等离子体离子（92,94）以更垂直的角度冲击侧壁表面（97,99）以增强蚀刻金属层（95）的侧壁表面（97,99）的蚀刻。
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公开(公告)号：US20080254617A1
公开(公告)日：2008-10-16
申请号：US11733519
申请日：2007-04-10
IPC分类号： H01L21/4763
CPC分类号： H01L21/76843 , H01L21/76873 , H01L21/76877 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device manufacturing process for forming a contact plug includes sequentially depositing a titanium or tantalum contact layer (30), a titanium nitride barrier layer (40), and a tungsten seed layer (50) in a contact opening (24). The contact hole (24) is then filled up from a bottom surface of the contact opening by electroplating a copper layer (60) so that no voids are formed in the contact opening (24). Any excess metal is removed with a CMP process to form the contact plugs (70), where the CMP process may also used to thin or remove one or more of the contact/seed/barrier layers (30, 40, 50).
摘要翻译： 用于形成接触插塞的半导体器件制造方法包括在接触开口（24）中顺序地沉积钛或钽接触层（30），氮化钛阻挡层（40）和钨籽晶层（50）。 接触孔（24）然后通过电镀铜层（60）从接触开口的底表面填充，使得在接触开口（24）中不形成空隙。 通过CMP工艺去除任何多余的金属以形成接触塞（70），其中CMP工艺也可以用于稀释或去除一个或多个接触/种子/阻挡层（30,40,50）。
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公开(公告)号：US07109079B2
公开(公告)日：2006-09-19
申请号：US11043337
申请日：2005-01-26
IPC分类号： H01L21/8238 , H01L29/76
CPC分类号： H01L21/823864 , H01L21/823835 , H01L21/823842
摘要： A method for forming a semiconductor device (100) includes a semiconductor substrate (102) having a first region (104), forming a gate dielectric (108) over the first region, forming a conductive metal oxide (110) over the gate dielectric, forming an oxidation resistant barrier layer (111) over the conductive metal oxide, and forming a capping layer over the oxidation resistant barrier layer. In one embodiment, the conductive metal oxide is IrO2, MoO2, and RuO2, and the oxidation resistant barrier layer includes TiN.
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公开(公告)号：US06933227B2
公开(公告)日：2005-08-23
申请号：US10691984
申请日：2003-10-23
CPC分类号： H01L21/28079 , H01L21/28088 , H01L29/495 , H01L29/4966 , H01L29/517 , H01L29/518 , H01L29/7833 , H01L2924/0002 , H01L2924/00
摘要： A process for forming a semiconductor structure includes forming a gate dielectric overlying a substrate, a conductive gate electrode overlying the gate dielectric, a barrier layer overlying and in physical contact with the conductive gate electrode, and an organic anti-reflective coating (ARC) layer overlying and in physical contact with the barrier layer.
摘要翻译： 一种用于形成半导体结构的工艺包括形成覆盖在衬底上的栅极电介质，覆盖栅极电介质的导电栅电极，覆盖并与导电栅电极物理接触的阻挡层，以及有机抗反射涂层（ARC）层 覆盖并与屏障层物理接触。
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公开(公告)号：US06902969B2
公开(公告)日：2005-06-07
申请号：US10632473
申请日：2003-07-31
申请人： Olubunmi O. Adetutu , Hsing H. Tseng , Wei E. Wu
发明人： Olubunmi O. Adetutu , Hsing H. Tseng , Wei E. Wu
IPC分类号： H01L21/8238
CPC分类号： H01L21/823842
摘要： A semiconductor device has a P channel gate stack comprising a first metal type and a second metal type over the first metal type and an N channel gate stack comprising the second metal type in direct contact with a gate dielectric/etch stop layer stack. The N channel gate stack and the P channel gate stack are etched by a dry etch. Either the gate dielectric or etch stop can be in contact with the substrate. The etch stop layer prevents the dry etch of the first and second metal layers from etching through the gate dielectric and gouging the underlying substrate.
摘要翻译： 半导体器件具有包括第一金属类型的第一金属类型和第二金属类型的P沟道栅极堆叠以及包括与栅极电介质/蚀刻停止层堆叠直接接触的第二金属类型的N沟道栅极堆叠。 通过干蚀刻蚀刻N沟道栅极堆叠和P沟道栅极堆叠。 栅极电介质或蚀刻停止件可以与衬底接触。 蚀刻停止层防止第一和第二金属层的干蚀刻蚀刻通过栅极电介质并且刨削下面的衬底。
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公开(公告)号：US06881681B2
公开(公告)日：2005-04-19
申请号：US10301993
申请日：2002-11-22
IPC分类号： C23C16/44 , H01L21/31 , H01L21/44 , H01L21/469
CPC分类号： C23C16/4401
摘要： Heating a reaction chamber or other apparatus in the absence of product wafers to a “curing” temperature above a deposition temperature between the deposition of a film on a first set of semiconductor product wafers and the deposition of a film on a second set of semiconductor product wafers. In some embodiments, a boat with filler wafers is in the reaction chamber when the reaction chamber is heated to the curing temperature. In some examples, the films are deposited by a low pressure chemical vapor deposition (LPCVD) process. With some processes, if the deposition of a film on product wafers is at a temperature below a certain temperature, the film deposited with the product wafer on a boat, filler wafers, and/or other structures in the reaction chamber can cause contamination of product wafers subsequently deposited with a film in the presence of the boat and filler wafers. Contamination from these previously deposited films is inhibited by applying a curing temperature to the deposited fillers in the absence of the product wafers before a film is deposited on the next set of product wafers.
摘要翻译： 在不存在产品晶片的情况下将反应室或其它装置加热到高于第一组半导体产品晶片上的膜的沉积和第二组半导体产品上的膜的沉积之后的沉积温度的“固化”温度 晶圆 在一些实施例中，当反应室被加热到固化温度时，具有填充物晶片的舟皿在反应室中。 在一些实例中，通过低压化学气相沉积（LPCVD）工艺沉积膜。 通过一些方法，如果在产品晶片上的膜沉积处于低于某一温度的温度，则沉积在产品晶片上的膜在反应室中的船，填料晶片和/或其它结构上可能导致产物污染 随后在存在船和填料晶片的情况下沉积薄膜。 在将膜沉积在下一组产品晶片之前，通过在不存在产品晶片的情况下将沉积的填料施加固化温度来抑制来自这些先前沉积的膜的污染。
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公开(公告)号：US08426310B2
公开(公告)日：2013-04-23
申请号：US12787296
申请日：2010-05-25
申请人： Olubunmi O. Adetutu , Ted R. White , Mark D. Hall
发明人： Olubunmi O. Adetutu , Ted R. White , Mark D. Hall
IPC分类号： H01L21/44
CPC分类号： H01L21/76895 , H01L21/76807 , H01L21/76808
摘要： A method for forming a shared contact in a semiconductor device having a gate electrode corresponding to a first transistor and a source/drain region corresponding to a second transistor is provided. The method includes forming a first opening in a dielectric layer overlying the gate electrode and the source/drain region, wherein the first opening extends substantially to the gate electrode corresponding to the first transistor. The method further includes after forming the first opening, forming a second opening, contiguous with the first opening, in the overlying dielectric layer, wherein the second opening extends substantially to the source/drain region corresponding to the second transistor. The method further includes forming the shared contact between the gate electrode corresponding to the first transistor and the source/drain region corresponding to the second transistor by filling the first opening and the second opening with a conductive material.
摘要翻译： 提供一种用于在具有对应于第一晶体管的栅电极和对应于第二晶体管的源/漏区的半导体器件中形成共用触点的方法。 该方法包括在覆盖栅电极和源极/漏极区的电介质层中形成第一开口，其中第一开口基本上延伸到对应于第一晶体管的栅电极。 该方法还包括在形成第一开口之后，在覆盖介质层中形成与第一开口邻接的第二开口，其中第二开口基本上延伸到对应于第二晶体管的源极/漏极区域。 该方法还包括通过用导电材料填充第一开口和第二开口来形成对应于第一晶体管的栅电极与对应于第二晶体管的源极/漏极区之间的共用接触。
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38.发明授权Electronic device comprising a gate electrode including a metal-containing layer having one or more impurities 有权电子器件包括含有含有一种或多种杂质的含金属层的栅电极公开(公告)号：US07868389B2
公开(公告)日：2011-01-11
申请号：US11928314
申请日：2007-10-30
IPC分类号： H01L29/76
CPC分类号： H01L21/823857 , H01L21/823842
摘要： One or more impurities may be incorporated within a metal-containing layer of a metal-containing gate electrode to modify the work function of the metal-containing gate electrode of a transistor can affect the threshold voltage of the transistor. In one embodiment, the impurity can be used in a p-channel transistor to allow the work function of a metal-containing gate electrode to be closer to the valence band for silicon. In another embodiment, the impurity can be used in an n-channel transistor to allow the work function of a metal-containing gate electrode to be closer to the conduction band for silicon. In a particular embodiment, a boron-containing species is implanted into a metal-containing layer within the metal-containing gate electrode within a p-channel transistor, so that the metal-containing gate electrode has a work function closer to the valence band for silicon as compared to the metal-containing gate electrode without the boron-containing species.
摘要翻译： 可以在含金属的栅电极的含金属层内并入一种或多种杂质以改变晶体管的含金属栅电极的功函数可影响晶体管的阈值电压。 在一个实施例中，杂质可用于p沟道晶体管，以允许含金属的栅电极的功函数更接近硅的价带。 在另一实施例中，杂质可用于n沟道晶体管，以允许含金属的栅电极的功函数更接近于硅的导带。 在一个具体的实施方案中，将含硼物质注入到在p沟道晶体管内的含金属栅电极内的含金属层中，使得含金属栅电极具有更接近价带的功函数 与没有含硼物质的含金属栅电极相比。
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公开(公告)号：US20090142895A1
公开(公告)日：2009-06-04
申请号：US11948209
申请日：2007-11-30
IPC分类号： H01L21/8234
CPC分类号： H01L21/823871 , H01L21/76897 , H01L21/823468 , H01L21/823475 , H01L29/665
摘要： A method for forming a via includes forming a gate electrode over a semiconductor substrate, forming a source/drain region in the semiconductor substrate adjacent the gate electrode, forming a silicide region in the source/drain region, forming a post-silicide spacer adjacent the gate electrode after forming the silicide region, forming an interlayer dielectric layer over the gate electrode, the post-silicide spacer, and the silicide region, and forming a conductive via in the interlayer dielectric layer, extending to the silicide region.
摘要翻译： 形成通孔的方法包括在半导体衬底上形成栅电极，在与栅电极相邻的半导体衬底中形成源极/漏极区域，在源/漏区域中形成硅化物区域，形成邻近硅化物间隔区 在形成硅化物区域之后形成栅电极，在栅电极，硅化物间隔物和硅化物区域之上形成层间电介质层，并且在层间电介质层中形成延伸到硅化物区域的导电通孔。
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公开(公告)号：US20080248649A1
公开(公告)日：2008-10-09
申请号：US11697106
申请日：2007-04-05
IPC分类号： H01L21/311
CPC分类号： H01L21/31612 , H01L21/02164 , H01L21/02271 , H01L21/02362 , H01L21/31116 , H01L21/31144 , H01L21/3221 , H01L21/76816 , H01L21/76829 , H01L21/76832 , H01L21/76837 , H01L27/115 , H01L27/11521 , H01L2924/0002 , H01L2924/00
摘要： A method and apparatus are described for forming a first inter-layer dielectric (ILD0) stack having a protective gettering layer (72) with a substantially uniform thickness. After forming device components (32, 33) on a substrate (31), a gap fill dielectric layer of SATEOS (52) is deposited over an etch stop layer of PEN ESL (42) and then planarized before sequentially depositing a gettering layer of BPTEOS (72) and capping dielectric layer (82) on the planarized gap fill dielectric layer (52). Once the ILD0 stack is formed, one or more contact openings (92, 94, 96) are etched through the ILD0 stack, thereby exposing the etch stop layer (42) over the intended contact regions.
摘要翻译： 描述了一种用于形成具有基本均匀厚度的保护性吸气层（72）的第一层间电介质（ILD0）堆叠的方法和装置。 在衬底（31）上形成器件部件（32,33）之后，将SATEOS（52）的间隙填充电介质层沉积在PEN ESL（42）的蚀刻停止层上，然后在顺序沉积BPTEOS吸气层之前进行平坦化 （72）和在平坦化间隙填充介电层（52）上的覆盖电介质层（82）。 一旦形成了ILD0堆叠，就通过ILD0堆叠蚀刻一个或多个接触开口（92,94,96），从而将蚀刻停止层（42）暴露在预期的接触区域上。
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