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    SYSTEM, METHOD AND COMPUTER PROGRAM PRODUCT FOR PROVIDING A PROGRAMMABLE QUIESCE FILTERING REGISTER
    32.
    发明申请
    SYSTEM, METHOD AND COMPUTER PROGRAM PRODUCT FOR PROVIDING A PROGRAMMABLE QUIESCE FILTERING REGISTER 有权
    用于提供可编程QUIESCE FILTERING寄存器的系统，方法和计算机程序产品

    公开(公告)号：US20120144154A1

    公开(公告)日：2012-06-07

    申请号：US13372603

    申请日：2012-02-14

    申请人： Lisa C. Heller ,  Harald Boehm ,  Ute Gaertner ,  Timothy J. Slegel ,  Jennifer A. Navarro

    发明人： Lisa C. Heller ,  Harald Boehm ,  Ute Gaertner ,  Timothy J. Slegel ,  Jennifer A. Navarro

    IPC分类号： G06F12/10

    CPC分类号： G06F9/4812

    摘要： Storing translation lookaside buffer (TLB) entries are in a TLB1 at the processor. The TLB1 includes entries associated with main storage accesses of programs executing in a guest mode in a current zone and entries associated with main storage accesses of firmware executing in a host mode. A quiesce interruption request is received at the processor that includes a requesting zone indicator. The processor is either executing in the host mode and has no zone or in the guest mode with the current zone. The requesting zone indicator and the contents of a programmable filtering register that indicates exceptions to filtering performed by the processor is used to determine if filtering should be performed. The quiesce interruption request may be filtered based on the requesting zone indicator even after the mode switches from the guest mode to the host mode.

    摘要翻译： 存储翻译后备缓冲区（TLB）条目位于处理器的TLB1中。 TLB1包括与在当前区域中以访客模式执行的程序的主存储访问相关联的条目和与以主机模式执行的固件的主存储访问相关联的条目。 在包括请求区域指示符的处理器处接收到静默中断请求。 处理器正在主机模式下执行，并且没有区域，或者在访问模式下使用当前区域。 请求区域指示符和指示处理器执行的过滤异常的可编程过滤寄存器的内容用于确定是否应执行过滤。 即使模式从客户模式切换到主机模式，也可以基于请求区域指示符来过滤停顿中断请求。

    Dynamic Address Translation With Translation Exception Qualifier
    33.
    发明申请
    Dynamic Address Translation With Translation Exception Qualifier 有权
    动态地址转换与翻译异常限定符

    公开(公告)号：US20120084488A1

    公开(公告)日：2012-04-05

    申请号：US13312079

    申请日：2011-12-06

    申请人： Dan F. Greiner ,  Lisa C. Heller ,  Damian L. Osisek ,  Erwin Pfeffer

    发明人： Dan F. Greiner ,  Lisa C. Heller ,  Damian L. Osisek ,  Erwin Pfeffer

    IPC分类号： G06F12/10

    CPC分类号： G06F12/0284 ,  G06F3/0604 ,  G06F3/0667 ,  G06F3/067 ,  G06F9/455 ,  G06F12/10 ,  G06F12/1009 ,  G06F12/1036 ,  G06F12/109 ,  G06F2212/1032 ,  G06F2212/152 ,  G06F2212/50 ,  G06F2212/652 ,  G06F2212/657

    摘要： What is provided is an enhanced dynamic address translation facility. In one embodiment, a virtual address to be translated and an initial origin address of a translation table of the hierarchy of translation tables are obtained. Dynamic address translation of the virtual address proceeds. In response to a translation interruption having occurred during dynamic address translation, bits are stored in a translation exception qualifier (TXQ) field to indicate that the exception was either a host DAT exception having occurred while running a host program or a host DAT exception having occurred while running a guest program. The TXQ is further capable of indicating that the exception was associated with a host virtual address derived from a guest page frame real address or a guest segment frame absolute address. The TXQ is further capable of indicating that a larger or smaller host frame size is preferred to back a guest frame.

    摘要翻译： 提供的是增强的动态地址转换设施。 在一个实施例中，获得要转换的虚拟地址和翻译表的层次结构的转换表的初始起始地址。 虚拟地址的动态地址转换进行。 响应于在动态地址转换期间发生的翻译中断，比特被存储在转换异常限定符（TXQ）字段中，以指示异常是在运行主机程序或主机DAT异常发生时发生的主机DAT异常 同时运行一个客人程序。 TXQ还能够指示异常与从访客页面帧实际地址或访客段帧绝对地址导出的主机虚拟地址相关联。 TXQ还能够指示较大或较小的主机帧大小优于后端客机帧。

    Enhanced dynamic address translation with load real address function
    34.
    发明授权
    Enhanced dynamic address translation with load real address function 失效
    增强动态地址转换与负载实地址功能

    公开(公告)号：US08041922B2

    公开(公告)日：2011-10-18

    申请号：US11972705

    申请日：2008-01-11

    申请人： Dan F. Greiner ,  Lisa C. Heller ,  Damian L. Osisek ,  Erwin Pfeffer ,  Timothy J. Slegel ,  Gustav E. Sittmann

    发明人： Dan F. Greiner ,  Lisa C. Heller ,  Damian L. Osisek ,  Erwin Pfeffer ,  Timothy J. Slegel ,  Gustav E. Sittmann

    IPC分类号： G06F12/02

    CPC分类号： G06F12/1009 ,  G06F9/30043 ,  G06F9/30101 ,  G06F9/34 ,  G06F9/342 ,  G06F2212/651 ,  G06F2212/657

    摘要： What is provided is a load real address function defined for a machine architecture of a computer system. In one embodiment, a machine instruction containing an opcode is obtained indicating that a load real address is to be performed. The instruction further identifies a first general register. Based on the contents of the machine instruction, a virtual address to be translated is obtained. Dynamic address translation is performed on the virtual address to obtain a segment-frame absolute address of a large block of data in memory. If an extended DAT facility and a format control field in the segment table entry are enabled, the address of the block of data is saved in the first general register. A page index portion and a byte index portion of the virtual address may also be saved in the first general register.

    摘要翻译： 提供了为计算机系统的机器结构定义的负载实地址功能。 在一个实施例中，获得包含操作码的机器指令，指示要执行负载实际地址。 该指令进一步标识第一个通用寄存器。 根据机器指令的内容，获得要翻译的虚拟地址。 对虚拟地址执行动态地址转换，以获得存储器中大块数据的段帧绝对地址。 如果分段表项中的扩展DAT功能和格式控制字段被使能，数据块的地址将保存在第一个通用寄存器中。 虚拟地址的页索引部分和字节索引部分也可以保存在第一通用寄存器中。

    METHOD, SYSTEM AND COMPUTER PROGRAM PRODUCT FOR PROVIDING FILTERING OF GUEST2 QUIESCE REQUESTS
    36.
    发明申请
    METHOD, SYSTEM AND COMPUTER PROGRAM PRODUCT FOR PROVIDING FILTERING OF GUEST2 QUIESCE REQUESTS 失效
    方法，系统和计算机程序产品，用于提供GUEST2 QUIESCE要求的过滤

    公开(公告)号：US20090217264A1

    公开(公告)日：2009-08-27

    申请号：US12037887

    申请日：2008-02-26

    申请人： Lisa C. Heller ,  Damian L. Osisek ,  Charles F. Webb

    发明人： Lisa C. Heller ,  Damian L. Osisek ,  Charles F. Webb

    IPC分类号： G06F9/455

    CPC分类号： G06F9/45558 ,  G06F2009/45566

    摘要： A method, system and computer program product for providing filtering of level two guest (G2) quiesce requests. The method includes receiving a G2 quiesce interruption request at a processor currently or previously executing a G2 running under a level two hypervisor in a logical partition. The G2 includes a current zone and G2 virtual machine (VM) identifier. The quiesce interruption request specifies an initiating zone and an initiating G2 VM identifier. It is determined if the G2 quiesce interruption request can be filtered by the processor. The determining is responsive to the current G2 VM identifier, the current zone, the initiating zone and the initiating G2 VM identifier. The G2 quiesce interruption request is filtered at the processor in response to determining that the G2 quiesce interruption request can be filtered. Thus, filtering between G2 virtual machines running in the logical partition is provided.

    摘要翻译： 一种用于提供二级客户（G2）静默请求过滤的方法，系统和计算机程序产品。 该方法包括在当前或先前执行在逻辑分区中的二级虚拟机管理程序下运行的G2的处理器处接收G2停顿中断请求。 G2包括当前区域和G2虚拟机（VM）标识符。 静默中断请求指定启动区域和启动G2 VM标识符。 确定G2停顿中断请求是否可以被处理器过滤。 该确定响应于当前的G2 VM标识符，当前区域，起始区域和起始G2 VM标识符。 响应于确定可以过滤G2静默中断请求，在处理器处对G2静默中断请求进行过滤。 因此，提供了在逻辑分区中运行的G2虚拟机之间的过滤。

    DYNAMIC ADDRESS TRANSLATION WITH FRAME MANAGEMENT
    37.
    发明申请
    DYNAMIC ADDRESS TRANSLATION WITH FRAME MANAGEMENT 有权
    动态地址翻译与框架管理

    公开(公告)号：US20090187724A1

    公开(公告)日：2009-07-23

    申请号：US11972725

    申请日：2008-01-11

    申请人： DAN F. GREINER ,  Charles W. Gainey, JR. ,  Lisa C. Heller ,  Damian L. Osisek ,  Timothy J. Slegel ,  Gustav E. Sittmann

    发明人： DAN F. GREINER ,  Charles W. Gainey, JR. ,  Lisa C. Heller ,  Damian L. Osisek ,  Timothy J. Slegel ,  Gustav E. Sittmann

    IPC分类号： G06F12/00

    CPC分类号： G06F12/1475 ,  G06F9/3004 ,  G06F9/30047 ,  G06F9/30145 ,  G06F12/10

    摘要： What is disclosed is a set key and clear frame management function defined for a machine architecture of a computer system. In one embodiment, a machine instruction is obtained which identifies a first and second general register. Obtained from the first general register is a frame size field indicating whether a storage frame is one of a small block or a large block of data. Obtained from the second general register is an operand address of a storage frame upon which the instruction is to be performed. If the storage frame is a small block, the instruction is performed only on the small block. If the indicated storage frame is a large block of data, an operand address of an initial first block of data within the large block of data is obtained from the second general register. The frame management instruction is performed on all blocks starting from the initial first block.

    摘要翻译： 公开的是针对计算机系统的机器结构定义的集合关键和清晰的帧管理功能。 在一个实施例中，获得识别第一和第二通用寄存器的机器指令。 从第一通用寄存器获得的是指示存储帧是小块还是大块数据的帧大小字段。 从第二通用寄存器获得的是要执行指令的存储帧的操作数地址。 如果存储帧是小块，则仅在小块上执行指令。 如果指示的存储帧是大数据块，则从第二通用寄存器获得大数据块内的初始第一数据块的操作数地址。 在从初始第一块开始的所有块上执行帧管理指令。

    DYNAMIC ADDRESS TRANSLATION WITH LOAD PAGE TABLE ENTRY ADDRESS
    38.
    发明申请
    DYNAMIC ADDRESS TRANSLATION WITH LOAD PAGE TABLE ENTRY ADDRESS 有权
    动态地址转换与加载页表输入地址

    公开(公告)号：US20090182975A1

    公开(公告)日：2009-07-16

    申请号：US11972700

    申请日：2008-01-11

    申请人： DAN F. GREINER ,  Lisa C. Heller ,  Damian L. Osisek ,  Erwin Pfeffer ,  Timothy J. Slegel ,  Gustav E. Sittmann

    发明人： DAN F. GREINER ,  Lisa C. Heller ,  Damian L. Osisek ,  Erwin Pfeffer ,  Timothy J. Slegel ,  Gustav E. Sittmann

    IPC分类号： G06F12/10

    CPC分类号： G06F12/1027 ,  G06F12/1009 ,  G06F2212/651 ,  G06F2212/652

    摘要： What is provided is a load page table entry address function defined for a machine architecture of a computer system. In one embodiment, a machine instruction is obtained which contains an opcode indicating that a load page table entry address function is to be performed. The machine instruction contains an M field, a first field identifying a first general register, and a second field identifying a second general register. Based on the contents of the M field, an initial origin address of a hierarchy of address translation tables having at least one segment table is obtained. Based on the obtained initial origin address, dynamic address translation is performed until a page table entry is obtained. The page table entry address is saved in the identified first general register.

    摘要翻译： 提供了为计算机系统的机器结构定义的加载页表项地址函数。 在一个实施例中，获得机器指令，其中包含指示要执行加载页表项地址函数的操作码。 机器指令包含M字段，标识第一通用寄存器的第一字段和标识第二通用寄存器的第二字段。 基于M场的内容，获得具有至少一个段表的地址转换表的层次结构的初始起始地址。 基于获得的初始起始地址，执行动态地址转换，直到获得页表项。 页表入口地址保存在识别的第一个通用寄存器中。

    Dynamic address translation with fetch protection
    39.
    发明授权
    Dynamic address translation with fetch protection 有权
    动态地址转换带保护

    公开(公告)号：US08677098B2

    公开(公告)日：2014-03-18

    申请号：US11972688

    申请日：2008-01-11

    申请人： Dan F. Greiner ,  Charles W. Gainey, Jr. ,  Lisa C. Heller ,  Damian L. Osisek ,  Erwin Pfeffer ,  Timothy J. Slegel ,  Charles F. Webb

    发明人： Dan F. Greiner ,  Charles W. Gainey, Jr. ,  Lisa C. Heller ,  Damian L. Osisek ,  Erwin Pfeffer ,  Timothy J. Slegel ,  Charles F. Webb

    IPC分类号： G06F12/00 ,  G06F13/00 ,  G06F13/28

    CPC分类号： G06F12/1027 ,  G06F9/30047 ,  G06F12/0215 ,  G06F12/1009 ,  G06F12/1036 ,  G06F12/145 ,  G06F2212/1052 ,  G06F2212/654 ,  G06F2212/656 ,  G06F2212/68

    摘要： What is provided is an enhanced dynamic address translation facility. In one embodiment, a virtual address to be translated is first obtained and an initial origin address of a translation table of the hierarchy of translation tables is obtained. Based on the obtained initial origin, a segment table entry is obtained. The segment table entry is configured to contain a format control and access validity fields. If the format control and access validity fields are enabled, the segment table entry further contains an access control field, a fetch protection field, and a segment-frame absolute address. Store operations are permitted only if the access control field matches a program access key provided by any one of a Program Status Word or an operand of a program instruction being executed. Fetch operations are permitted if the program access key associated with the virtual address is equal to the segment access control field.

    摘要翻译： 提供的是增强的动态地址转换设施。 在一个实施例中，首先获得要被翻译的虚拟地址，并且获得翻译表层级的翻译表的初始起始地址。 基于获得的初始来源，获得段表条目。 段表项被配置为包含格式控制和访问有效性字段。 如果启用格式控制和访问有效性字段，则段表条目还包含访问控制字段，提取保护字段和段帧绝对地址。 仅当访问控制字段与程序状态字或正在执行的程序指令的操作数提供的程序访问键匹配时，才允许存储操作。 如果与虚拟地址相关联的程序访问密钥等于段访问控制字段，则允许获取操作。