公开(公告)号：US06819583B2

公开(公告)日：2004-11-16

申请号：US10345726

申请日：2003-01-15

申请人： Sheng Teng Hsu ,  Tingkai Li ,  Fengyan Zhang

发明人： Sheng Teng Hsu ,  Tingkai Li ,  Fengyan Zhang

IPC分类号： G11C1122

CPC分类号： G11C11/22

摘要： A ferroelectric thin film resistor memory array is formed on a substrate and includes plural memory cells arranged in an array of rows and columns; wherein each memory cell includes: a FE resistor having a pair of terminals, and a transistor associated with each resistor, wherein each transistor has a gate, a drain and a source, and wherein the drain of each transistor is electrically connected to one terminal of its associated resistor; a word line connected to the gate of each transistor in a row; a programming line connected to each memory cell in a column; and a bit line connected to each memory cell in a column.

摘要翻译： 铁基薄膜电阻存储阵列形成在基板上，并且包括以行和列为阵列排列的多个存储单元; 其中每个存储器单元包括：具有一对端子的FE电阻器和与每个电阻器相关联的晶体管，其中每个晶体管具有栅极，漏极和源极，并且其中每个晶体管的漏极电连接到 其相关电阻器; 连接到每个晶体管的栅极的字线; 连接到列中的每个存储单元的编程线; 以及连接到列中每个存储单元的位线。

公开(公告)号：US06759250B2

公开(公告)日：2004-07-06

申请号：US10196503

申请日：2002-07-15

申请人： Fengyan Zhang ,  Tingkai Li ,  Sheng Teng Hsu

发明人： Fengyan Zhang ,  Tingkai Li ,  Sheng Teng Hsu

IPC分类号： H01L2100

CPC分类号： H01L28/56 ,  H01L21/31604 ,  H01L21/31691 ,  H01L28/75

摘要： The ferroelectric structure including a Pt/Ir layered electrode used in conjunction with a lead germanate (Pb5Ge3O11) thin film is provided. The electrode exhibits good adhesion to the substrate, and barrier properties resistant to oxygen and lead. Ferroelectric properties are improved, without detriment to the leakage current, by using a thin IrO2 layer formed in situ, during the MOCVD lead germanate (Pb5Ge3O11) thin film process. By using a Pt/Ir electrode, a relatively low MOCVD processing temperature is required to achieve c-axis oriented lead germanate (Pb5Ge3O11) thin film. The temperature range of MOCVD c-axis oriented lead germanate (Pb5Ge3O11) thin film on top of Pt/Ir is 400-500° C. Further, a relatively large nucleation density is obtained, as compared to using single-layer iridium electrode. Therefore, the lead germanate (Pb5Ge3O11) thin film has a smooth surface, a homogeneous microstructure, and homogeneous ferroelectric properties. A method of forming the above-mentioned multi-layered electrode ferroelectric structure is also provided.

摘要翻译： 提供了包括与锗酸铅（Pb5Ge3O11）薄膜结合使用的Pt / Ir层叠电极的铁电体结构。 该电极对基材表现出良好的粘合性，并且对氧和铅具有阻挡性能。 在MOCVD锗酸铅（Pb5Ge3O11）薄膜工艺中，通过使用在原位形成的薄的IrO 2层，铁电性能得到改善，而不损害漏电流。 通过使用Pt / Ir电极，需要相对低的MOCVD处理温度来实现c轴取向的锗酸铅（Pb5Ge3O11）薄膜。 Pt / Ir顶部的MOCVD c轴取向锗酸铅（Pb5Ge3O11）薄膜的温度范围为400-500℃。与使用单层铱电极相比，获得了较大的成核密度。 因此，锗酸铅（Pb5Ge3O11）薄膜表面光滑，微观组织均匀，铁电性能均匀。 还提供了形成上述多层电极铁电体结构体的方法。

公开(公告)号：US06664116B2

公开(公告)日：2003-12-16

申请号：US10020868

申请日：2001-12-12

申请人： Tingkai Li ,  Sheng Teng Hsu

发明人： Tingkai Li ,  Sheng Teng Hsu

IPC分类号： H01L2100

CPC分类号： H01L21/28273 ,  C23C16/0272 ,  C23C16/40 ,  C23C16/56 ,  H01L21/28194 ,  H01L21/28291 ,  H01L21/31691 ,  H01L28/56 ,  H01L29/513 ,  H01L29/517

摘要： A method of forming a ferroelectric thin film on a high-k layer includes preparing a silicon substrate; forming a high-k layer on the substrate; depositing a seed layer of ferroelectric material at a relatively high temperature on the high-k layer; depositing a top layer of ferroelectric material on the seed layer at a relatively low temperature; and annealing the substrate, the high-k layer and the ferroelectric layers to form a ferroelectric thin film.

摘要翻译： 在高k层上形成铁电薄膜的方法包括：制备硅衬底; 在基板上形成高k层; 在高k层上沉积相对较高温度的铁电材料种子层; 在相对低的温度下在种子层上沉积铁电材料的顶层; 并且对衬底，高k层和铁电层进行退火以形成铁电薄膜。

公开(公告)号：US06566148B2

公开(公告)日：2003-05-20

申请号：US09929710

申请日：2001-08-13

申请人： Sheng Teng Hsu ,  Tingkai Li ,  Bruce D. Ulrich

发明人： Sheng Teng Hsu ,  Tingkai Li ,  Bruce D. Ulrich

IPC分类号： H01L2100

CPC分类号： H01L27/11502 ,  H01L21/28291 ,  H01L27/11585 ,  H01L27/1159 ,  H01L29/6684

摘要： A method of making a ferroelectric memory transistor includes preparing a silicon substrate including forming plural active areas thereon; depositing a layer of gate insulator on the substrate, and depositing a layer of polysilicon over the gate insulator layer; forming a source region, a drain region and a gate electrode; depositing a layer of bottom electrode material and finishing the bottom electrode without damaging the underlying gate insulator and silicon substrate; depositing a layer of ferroelectric material on the bottom electrode; depositing a layer of top electrode material on the ferroelectric material; and finishing the transistor, including passivation oxide deposition, contact hole etching and metalization.

摘要翻译： 制造铁电存储晶体管的方法包括制备包括在其上形成多个有源区的硅衬底; 在所述衬底上沉积栅极绝缘体层，以及在所述栅极绝缘体层上沉积多晶硅层; 形成源极区域，漏极区域和栅极电极; 沉积一层底部电极材料并整理底部电极，而不损坏下面的栅极绝缘体和硅衬底; 在底部电极上沉​​积一层铁电材料; 在铁电材料上沉积顶层电极材料层; 并整理晶体管，包括钝化氧化物沉积，接触孔蚀刻和金属化。

公开(公告)号：US06531324B2

公开(公告)日：2003-03-11

申请号：US09820039

申请日：2001-03-28

申请人： Sheng Teng Hsu ,  Fengyan Zhang ,  Tingkai Li

发明人： Sheng Teng Hsu ,  Fengyan Zhang ,  Tingkai Li

IPC分类号： H01L2100

CPC分类号： H01L29/516 ,  H01L21/28291 ,  H01L29/78391

摘要： A ferroelectric transistor gate structure with a ferroelectric gate and passivation sidewalls is provided. The passivation sidewalls serve as an insulator to reduce, or eliminate, the diffusion of oxygen or hydrogen into the ferroelectric gate. A method of forming the ferroelectric gate structure is also provided. The method comprises the steps of forming a sacrificial gate structure, removing the sacrificial gate structure, depositing passivation insulator material, etching the passivation insulator material using anisotropic plasma etching to form passivation sidewalls, depositing a ferroelectric material, polishing the ferroelectric material using CMP, and forming a top electrode overlying the ferroelectric material.

公开(公告)号：US06495378B2

公开(公告)日：2002-12-17

申请号：US09814273

申请日：2001-03-21

申请人： Tingkai Li ,  Fengyan Zhang ,  Yoshi Ono ,  Sheng Teng Hsu

发明人： Tingkai Li ,  Fengyan Zhang ,  Yoshi Ono ,  Sheng Teng Hsu

IPC分类号： H01L2100

CPC分类号： H01L21/02197 ,  C23C16/40 ,  H01L21/02271 ,  H01L21/31604 ,  H01L21/31691

摘要： A Pb3GeO5 phase PGO thin film is provided. This film has ferroelastic properties that make it ideal for many microelectromechanical applications or as decoupling capacitors in high speed multichip modules. This PGO film is uniquely formed in a MOCVD process that permits a thin film, less than 1 mm, of material to be deposited. The process mixes Pd and germanium in a solvent. The solution is heated to form a precursor vapor which is decomposed. The method provides deposition temperatures and pressures. The as-deposited film is also annealed to enhanced the film's ferroelastic characteristics. A ferroelastic capacitor made from the present invention PGO film is also provided.

摘要翻译： 提供Pb3GeO5相PGO薄膜。 该薄膜具有铁弹性，使其成为许多微机电应用或高速多芯片模块中的去耦电容器的理想选择。 该PGO膜在MOCVD工艺中唯一形成，其允许沉积小于1mm的薄膜。 该方法将Pd和锗在溶剂中混合。 将溶液加热以形成分解的前体蒸汽。 该方法提供沉积温度和压力。 沉积的膜也被退火以增强膜的铁弹性特征。 还提供了由本发明PGO膜制成的铁弹性电容器。

公开(公告)号：US06190925B1

公开(公告)日：2001-02-20

申请号：US09302272

申请日：1999-04-28

申请人： Tingkai Li ,  Fengyan Zhang ,  Yoshi Ono ,  Sheng Teng Hsu

发明人： Tingkai Li ,  Fengyan Zhang ,  Yoshi Ono ,  Sheng Teng Hsu

IPC分类号： H01L2100

CPC分类号： H01L21/31604 ,  C23C16/40 ,  H01L21/31691 ,  Y10S438/933

摘要： The present invention provides a substantially single crystal PGO film with optimal the ferroelectric properties. The PGO film and adjacent electrodes are epitaxially grown to minimize mismatch between the structures. MOCVD deposition methods and RTP annealing procedures permit a PGO film to be epitaxially grown in commercial fabrication processes. These epitaxial ferroelectric have application in FeRAM memory devices. The present invention deposition method epitaxially grows ferroelectric Pb5Ge3O11 thin films along with c-axis orientation.

摘要翻译： 本发明提供了具有最佳铁电性能的基本单晶PGO膜。 PGO膜和相邻电极被外延生长以最小化结构之间的失配。 MOCVD沉积方法和RTP退火程序允许PGO膜在商业制造工艺中外延生长。 这些外延铁电体已经应用于FeRAM存储器件中。 本发明沉积方法外延生长铁电Pb5Ge3O11薄膜以及c轴取向。

公开(公告)号：US07811837B2

公开(公告)日：2010-10-12

申请号：US11582275

申请日：2006-10-16

申请人： Tingkai Li ,  Wei Gao ,  Yoshi Ono ,  Sheng Teng Hsu

发明人： Tingkai Li ,  Wei Gao ,  Yoshi Ono ,  Sheng Teng Hsu

IPC分类号： H01L29/00

CPC分类号： H01L27/15 ,  H01L33/0004 ,  H01L33/343

摘要： A method of fabricating an electroluminescent device includes, on a prepared substrate, depositing a rare earth-doped silicon-rich layer on gate oxide layer as a light emitting layer; and annealing and oxidizing the structure to repair any damage caused to the rare earth-doped silicon-rich layer; and incorporating the electroluminescent device into a CMOS IC. An electroluminescent device fabricated according to the method of the invention includes a substrate, a rare earth-doped silicon-rich layer formed on the gate oxide layer for emitting a light of a pre-determined wavelength; a top electrode formed on the rare earth-doped silicon-rich layer; and associated CMOS IC structures fabricated thereabout.

摘要翻译： 一种制造电致发光器件的方法包括：在制备的衬底上，在作为发光层的栅极氧化物层上沉积稀土掺杂的富硅层; 并对该结构进行退火和氧化以修复对稀土掺杂的富硅层造成的任何损伤; 并将电致发光器件并入CMOS IC。 根据本发明的方法制造的电致发光器件包括：衬底，形成在栅极氧化物层上的用于发射预定波长的光的稀土掺杂富硅层; 在稀土掺杂的富硅层上形成的顶部电极; 并在其附近制造相关的CMOS IC结构。

公开(公告)号：US07696550B2

公开(公告)日：2010-04-13

申请号：US11805177

申请日：2007-05-22

申请人： Tingkai Li ,  Lawrence J. Charneski ,  Wei-Wei Zhuang ,  David R. Evans ,  Sheng Teng Hsu

发明人： Tingkai Li ,  Lawrence J. Charneski ,  Wei-Wei Zhuang ,  David R. Evans ,  Sheng Teng Hsu

IPC分类号： H01L29/76

CPC分类号： H01L45/04 ,  H01L45/1233 ,  H01L45/147 ,  H01L45/1616

摘要： A multi-layer PrxCa1-xMnO3 (PCMO) thin film capacitor and associated deposition method are provided for forming a bipolar switching thin film. The method comprises: forming a bottom electrode; depositing a nanocrystalline PCMO layer; depositing a polycrystalline PCMO layer; forming a multi-layer PCMO film with bipolar switching properties; and, forming top electrode overlying the PCMO film. If the polycrystalline layers are deposited overlying the nanocrystalline layers, a high resistance can be written with narrow pulse width, negative voltage pulses. The PCMO film can be reset to a low resistance using a narrow pulse width, positive amplitude pulse. Likewise, if the nanocrystalline layers are deposited overlying the polycrystalline layers, a high resistance can be written with narrow pulse width, positive voltage pulses, and reset to a low resistance using a narrow pulse width, negative amplitude pulse.

摘要翻译： 提供多层PrxCa1-xMnO3（PCMO）薄膜电容器和相关的沉积方法用于形成双极开关薄膜。 该方法包括：形成底部电极; 沉积纳米晶体PCMO层; 沉积多晶PCMO层; 形成具有双极开关特性的多层PCMO膜; 并且形成覆盖PCMO膜的顶部电极。 如果多晶层沉积在纳米晶层之上，则可以用窄脉冲宽度，负电压脉冲写入高电阻。 PCMO膜可以使用窄脉冲宽度，正幅度脉冲复位为低电阻。 同样，如果纳米晶层沉积在多晶层上，则可以用窄脉冲宽度，正电压脉冲写入高电阻，并使用窄脉冲宽度，负幅度脉冲将其复位为低电阻。

公开(公告)号：US07446010B2

公开(公告)日：2008-11-04

申请号：US11435669

申请日：2006-05-17

申请人： Tingkai Li ,  Sheng Teng Hsu ,  David R. Evans

发明人： Tingkai Li ,  Sheng Teng Hsu ,  David R. Evans

IPC分类号： H01L21/8222

CPC分类号： H01L27/101 ,  G11C13/0007 ,  G11C2213/31 ,  H01L27/2409 ,  H01L29/66143 ,  H01L29/872 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/147

摘要： A method is provided for forming a metal/semiconductor/metal (MSM) back-to-back Schottky diode from a silicon (Si) semiconductor. The method deposits a Si semiconductor layer between a bottom electrode and a top electrode, and forms a MSM diode having a threshold voltage, breakdown voltage, and on/off current ratio. The method is able to modify the threshold voltage, breakdown voltage, and on/off current ratio of the MSM diode in response to controlling the Si semiconductor layer thickness. Generally, both the threshold and breakdown voltage are increased in response to increasing the Si thickness. With respect to the on/off current ratio, there is an optimal thickness. The method is able to form an amorphous Si (a-Si) and polycrystalline Si (polySi) semiconductor layer using either chemical vapor deposition (CVD) or DC sputtering. The Si semiconductor can be doped with a Group V donor material, which decreases the threshold voltage and increases the breakdown voltage.

摘要翻译： 提供了用于从硅（Si）半导体形成金属/半导体/金属（MSM）背对背肖特基二极管的方法。 该方法在底电极和顶电极之间沉积Si半导体层，并形成具有阈值电压，击穿电压和开/关电流比的MSM二极管。 响应于控制Si半导体层厚度，该方法能够修改MSM二极管的阈值电压，击穿电压和导通/截止电流比。 通常，响应于Si厚度的增加，阈值和击穿电压都增加。 关于开/关电流比，存在最佳厚度。 该方法能够使用化学气相沉积（CVD）或DC溅射形成非晶Si（a-Si）和多晶硅（polySi）半导体层。 Si半导体可以掺杂有V族施主材料，其降低阈值电压并增加击穿电压。