Address multiplexed dynamic RAM having a test mode capability
    33.
    发明授权
    Address multiplexed dynamic RAM having a test mode capability 失效
    地址复用动态RAM具有测试模式能力

    公开(公告)号:US5331596A

    公开(公告)日:1994-07-19

    申请号:US887802

    申请日:1992-05-26

    CPC分类号: G11C29/46 G01R31/31701

    摘要: An address multiplexed dynamic random access memory (RAM) which has both a normal operation mode and a test mode capability is provided. The test mode is initiated in response to particular signal level combinations of both the row address strobe (RAS) and column address strobe (CAS) signals and the write enable (WE) signal. Since the signal level combinations employed in connection with implementing the test mode are unused in the normal operating mode of the dynamic RAM, additional external terminals are unneeded. This dynamic RAM employs multiplexing circuitry on both the input side as well as on the output side of the dynamic RAM, which multiplexing circuitry is controlled during normal operation by select signals from a decoder and during the test mode by a test signal which allows accessing of data at all of the common complementary data lines by the testing circuitry so as to determine whether there is consistency or inconsistency of the data being read out for testing.

    摘要翻译: 提供具有正常操作模式和测试模式能力的地址多路复用动态随机存取存储器(RAM)。 响应于行地址选通(&upbar&R)和列地址选通(&upbar&C)信号和写使能(&upbar&W)信号的特定信号电平组合,启动测试模式。 由于在动态RAM的正常操作模式中不使用与实现测试模式相关的信号电平组合,因此不需要额外的外部终端。 该动态RAM在动态RAM的输入侧和输出侧都采用多路复用电路,该复用电路在正常操作期间通过来自解码器的选择信号以及在测试模式期间通过允许访问的测试信号 通过测试电路在所有公共补充数据线上的数据,以便确定正在读出的用于测试的数据是否一致或不一致。

    Semiconductor memory having multiple level storage structure
    35.
    发明授权
    Semiconductor memory having multiple level storage structure 失效
    具有多级存储结构的半导体存储器

    公开(公告)号:US4661929A

    公开(公告)日:1987-04-28

    申请号:US686018

    申请日:1984-12-24

    摘要: In a semiconductor memory includes a memory array consisting of a plurality of memory cells respectively having at least one storage capacitor, an addressing circuit which designates location of each memory cell, data lines which transmit data connected to said memory cells and data writing and reading circuits connected to said data lines. The semiconductor memory has a multiple level storage structure. In particular, the memory includes an arrangement for sequentially applying, on a time series basis, different voltages of at least 3 levels or more to the gate of a switching MOS transistor of said memory cells, a bias charge supplying means as said data reading circuit and a column register providing at least two or more storage cells which temporarily store said data.

    摘要翻译: 在半导体存储器中,包括由分别具有至少一个存储电容器的多个存储器单元组成的存储器阵列,指定每个存储单元的位置的寻址电路,发送连接到所述存储单元的数据的数据线和数据写入和读取电路 连接到所述数据线。 半导体存储器具有多级存储结构。 具体而言,该存储器包括用于按时间序列依次将至少3级以上的不同电压施加到所述存储单元的开关型MOS晶体管的栅极的装置,作为所述数据读取电路的偏置电荷供给装置 以及提供临时存储所述数据的至少两个或更多个存储单元的列寄存器。

    Semiconductor memory device
    37.
    发明授权
    Semiconductor memory device 失效
    半导体存储器件

    公开(公告)号:US06864559B2

    公开(公告)日:2005-03-08

    申请号:US10377717

    申请日:2003-03-04

    摘要: Disclosed is a semiconductor device, such as a semiconductor memory device, having structure wherein invasion of minority carriers from the semiconductor substrate into components of the device, formed on the substrate, can be avoided. The semiconductor memory device can be an SRAM or DRAM, for example, and includes a memory array and peripheral circuit on a substrate. In one aspect of the present invention, a buried layer of the same conductivity type as that of the substrate, but with a higher impurity concentration than that of the substrate, is provided beneath at least one of the peripheral circuit and memory array. A further region can extend from the buried layer, for example, to the surface of the semiconductor substrate, the buried layer and further region in combination acting as a shield to prevent minority carriers from penetrating to the device elements. As a second aspect of the present invention, first carrier absorbing areas (to absorb minority carriers) are located between the memory array and the switching circuit of the peripheral circuit, and second carrier absorbing areas are provided to surround input protective elements of the device. As a third embodiment of the present invention, a plurality of isolation regions of the same conductivity type are provided, with unequal voltages applied to these isolation regions, or unequal voltages applied to the substrate, on the one hand, and to these isolation regions, on the other.

    摘要翻译: 公开了一种半导体器件,例如半导体存储器件,其结构可以避免少数载流子从半导体衬底侵入形成在衬底上的器件的部件。 半导体存储器件例如可以是SRAM或DRAM,并且在衬底上包括存储器阵列和外围电路。 在本发明的一个方面中,在外围电路和存储器阵列中的至少一个之下提供与衬底相同的导电类型但具有比衬底的杂质浓度更高的杂质浓度的掩埋层。 另外的区域可以例如从掩埋层延伸到半导体衬底的表面,掩埋层和组合的另外的区域用作屏蔽以防止少数载流子穿透到器件元件。 作为本发明的第二方面,第一载流子吸收区域(以吸收少数载流子)位于存储器阵列和外围电路的开关电路之间,并且第二载流子吸收区域被设置为环绕该器件的输入保护元件。 作为本发明的第三实施例,提供了相同导电类型的多个隔离区域,一方面施加到这些隔离区域的不同电压或施加到基板的不同电压以及这些隔离区域, 在另一。

    Semiconductor memory device having separately biased wells for isolation
    38.
    发明授权
    Semiconductor memory device having separately biased wells for isolation 失效
    半导体存储器件具有单独偏置的阱用于隔离

    公开(公告)号:US5497023A

    公开(公告)日:1996-03-05

    申请号:US352238

    申请日:1994-12-08

    摘要: Disclosed is a semiconductor device, such as a semiconductor memory device, having structure wherein invasion of minority carriers from the semiconductor substrate into components of the device, formed on the substrate, can be avoided. The semiconductor memory device can be an SRAM or DRAM, for example, and includes a memory array and peripheral circuit on a substrate. In one aspect of the present invention, a buried layer of the same conductivity type as that of the substrate, but with a higher impurity concentration than that of the substrate, is provided beneath at least one of the peripheral circuit and memory array. A further region can extend from the buried layer, for example, to the surface of the semiconductor substrate, the buried layer and further region in combination acting as a shield to prevent minority carriers from penetrating to the device elements. As a second aspect of the present invention, first carrier absorbing areas (to absorb minority carriers) are located between the memory array and the switching circuit of the peripheral circuit, and second carrier absorbing areas are provided to surround input protective elements of the device. As a third embodiment of the present invention, a plurality of isolation regions of the same conductivity type are provided, with unequal voltages applied to these isolation regions, or unequal voltages applied to the substrate, on the one hand, and to these isolation regions, on the other.

    摘要翻译: 公开了一种半导体器件,例如半导体存储器件,其结构可以避免少数载流子从半导体衬底侵入形成在衬底上的器件的部件。 半导体存储器件例如可以是SRAM或DRAM,并且在衬底上包括存储器阵列和外围电路。 在本发明的一个方面中,在外围电路和存储器阵列中的至少一个之下提供与衬底相同的导电类型但具有比衬底的杂质浓度更高的杂质浓度的掩埋层。 另外的区域可以例如从掩埋层延伸到半导体衬底的表面,掩埋层和组合的另外的区域用作屏蔽以防止少数载流子穿透到器件元件。 作为本发明的第二方面,第一载流子吸收区域(以吸收少数载流子)位于存储器阵列和外围电路的开关电路之间,并且第二载流子吸收区域被设置为环绕该器件的输入保护元件。 作为本发明的第三实施例,提供了相同导电类型的多个隔离区域,一方面施加到这些隔离区域的不同电压或施加到基板的不同电压以及这些隔离区域, 在另一。

    Method of testing an address multiplexed dynamic RAM
    39.
    发明授权
    Method of testing an address multiplexed dynamic RAM 失效
    测试地址多路复用动态RAM的方法

    公开(公告)号:US5467314A

    公开(公告)日:1995-11-14

    申请号:US277430

    申请日:1994-07-18

    CPC分类号: G11C29/46 G01R31/31701

    摘要: In an address multiplexed dynamic random access memory (RAM) which has both a normal operation mode and a test mode capability, the test mode is initiated in response to particular signal level combinations of both the row address strobe (RAS) and column address strobe (CAS) signals and the write enable (WE) signal. Since the signal level combinations employed in connection with implementing the test mode are unused in the normal operating mode of the dynamic RAM, additional external terminals are unneeded. This dynamic RAM employs multiplexing circuitry on both the input side as well as on the output side of the dynamic RAM, which multiplexing circuitry is controlled during normal operation by select signals from a decoder and during the test mode by a test signal which allows accessing of data at all of the common complementary data lines by the testing circuitry so as to determine whether there is consistency or inconsistency of the data being read out for testing.

    摘要翻译: 在具有正常操作模式和测试模式能力的地址多路复用动态随机存取存储器(RAM)中,测试模式是响应于行地址选通(& Upbar&R)和列地址选通 (&upbar&C)信号和写使能(&upbar&W)信号。 由于在动态RAM的正常操作模式中不使用与实现测试模式相关的信号电平组合,因此不需要额外的外部终端。 该动态RAM在动态RAM的输入侧和输出侧都采用多路复用电路,该复用电路在正常操作期间通过来自解码器的选择信号以及在测试模式期间通过允许访问的测试信号 通过测试电路在所有公共补充数据线上的数据,以便确定正在读出的用于测试的数据是否一致或不一致。

    Data processor for selective simultaneous execution of a delay slot
instruction and a second subsequent instruction the pair following a
conditional branch instruction
    40.
    发明授权
    Data processor for selective simultaneous execution of a delay slot instruction and a second subsequent instruction the pair following a conditional branch instruction 失效
    用于选择性地同时执行延迟槽指令的数据处理器和在条件分支指令之后的第二后续指令

    公开(公告)号:US5381531A

    公开(公告)日:1995-01-10

    申请号:US727581

    申请日:1991-07-09

    IPC分类号: G06F9/38

    摘要: An instruction fetch unit (640) of a data processor (610) capable of simultaneous execution of two instructions fetches a first and a second instruction from a memory (620) in one cycle. The first and the second instruction thus fetched are set in a first and a second register (641, 642) before being decoded in a first and a second instruction decoder (644, 645). Comparators (131, 132) compares data on the destination field of the first instruction with data on the source field of the second instruction. When both the data are inconsistent, a parallel operation control unit (646) permits the first and the second instruction execution unit (651, 652) under the first and the second instruction to execute the two instructions in response to the outputs of the comparators (131, 132). When both the data are consistent, the parallel operation control unit (646) inhibits the parallel execution.

    摘要翻译: 能够同时执行两个指令的数据处理器(610)的指令获取单元(640)在一个周期中从存储器(620)获取第一和第二指令。 在第一和第二指令解码器(644,645)中被解码之前,这样取得的第一和第二指令被设置在第一和第二寄存器(641,642)中。 比较器(131,132)将第一指令的目的地字段的数据与第二指令的源字段上的数据进行比较。 当两个数据不一致时,并行操作控制单元(646)允许第一和第二指令下的第一和第二指令执行单元(651,652)响应于比较器的输出执行两个指令( 131,132)。 当两个数据一致时,并行操作控制单元(646)禁止并行执行。