公开(公告)号：US20080185644A1

公开(公告)日：2008-08-07

申请号：US11539288

申请日：2006-10-06

申请人： Brent A. Anderson ,  Andres Bryant ,  Edward J. Nowak ,  Richard Q. Williams

发明人： Brent A. Anderson ,  Andres Bryant ,  Edward J. Nowak ,  Richard Q. Williams

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/78612 ,  H01L29/66772 ,  H01L29/78621 ,  H01L29/78648

摘要： A FET has a shallow source/drain region, a deep channel region, a gate stack and a back gate that is surrounded by dielectric. The FET structure also includes halo or pocket implants that extend through the entire depth of the channel region. Because a portion of the halo and well doping of the channel is deeper than the source/drain depth, better threshold voltage and process control is achieved. A back-gated FET structure is also provided having a first dielectric layer in this structure that runs under the shallow source/drain region between the channel region and the back gate. This first dielectric layer extends from under the source/drain regions on either side of the back gate and is in contact with a second dielectric such that the back gate is bounded on each side or isolated by dielectric.

摘要翻译： FET具有浅电源/漏极区域，深沟道区域，栅极堆叠和被电介质包围的背栅极。 FET结构还包括延伸通过通道区域的整个深度的晕或凹坑植入物。 因为沟道的一部分光晕和阱掺杂比源极/漏极深度更深，所以实现了更好的阈值电压和过程控制。 还提供了后栅化FET结构，其具有在该结构中的第一介电层，其在沟道区域和后栅极之间的浅源极/漏极区域下方延伸。 该第一电介质层从背栅的两侧的源极/漏极区下方延伸并与第二电介质接触，使得后栅极在每一侧上界定或通过电介质隔离。

公开(公告)号：US07345334B2

公开(公告)日：2008-03-18

申请号：US10908081

申请日：2005-04-27

申请人： Edward J. Nowak ,  Richard Q. Williams

发明人： Edward J. Nowak ,  Richard Q. Williams

IPC分类号： H01L29/72

CPC分类号： H01L27/1203 ,  H01L27/0805 ,  H01L29/94

摘要： A semiconductor structure that may be a discrete capacitor, a Silicon On Insulator (SOI) Integrated Circuit (IC) including circuits with discrete such capacitors and/or decoupled by such discrete capacitors and an on-chip decoupling capacitor (decap). One capacitor plate may be a well (N-well or P-well) in a silicon bulk layer or a thickened portion of a surface silicon layer. The other capacitor plate may be doped polysilicon and separated from the first capacitor plate by capacitor dielectric, e.g., CVD or thermal oxide. Contacts to each of the capacitor plates directly connect and extend from the respective plates, such that direct contact is available from both plates.

摘要翻译： 可以是分立电容器的半导体结构，包括具有离散这种电容器的电路和/或由这种分立电容器去耦合的片上绝缘体（SOI）集成电路（IC）和片上去耦电容器（decap））。 一个电容器板可以是硅本体层中的阱（N阱或P阱）或表面硅层的增厚部分。 另一个电容器板可以是掺杂多晶硅并且通过电容器电介质例如CVD或热氧化物与第一电容器板分离。 与每个电容器板的接触件从相应的板直接连接和延伸，使得从两个板可以直接接触。

公开(公告)号：US06472230B2

公开(公告)日：2002-10-29

申请号：US10102381

申请日：2002-03-20

申请人： Kurt R. Kimmel ,  J. Alex Chediak ,  William T. Motsiff ,  Wilbur D. Pricer ,  Richard Q. Williams

发明人： Kurt R. Kimmel ,  J. Alex Chediak ,  William T. Motsiff ,  Wilbur D. Pricer ,  Richard Q. Williams

IPC分类号： H01L2100

CPC分类号： H01L23/5258 ,  G11C11/5607 ,  G11C2216/26 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method and structure for a programmable circuit that includes a magnetic device having a reluctance which is alterable.

摘要翻译： 一种用于可编程电路的方法和结构，其包括具有可改变的磁阻的磁性装置。

公开(公告)号：US06256184B1

公开(公告)日：2001-07-03

申请号：US09334088

申请日：1999-06-16

申请人： Robert J. Gauthier Jr. ,  Edward J. Nowak ,  Steven H. Voldman ,  Richard Q. Williams

发明人： Robert J. Gauthier Jr. ,  Edward J. Nowak ,  Steven H. Voldman ,  Richard Q. Williams

IPC分类号： H02H322

CPC分类号： H01L27/0251 ,  H01L27/0266

摘要： An ESD protection method and apparatus are provided for an IC chip having an I/O pad and I/O circuitry coupled to the I/O pad. A low threshold voltage FET is coupled to the I/O pad in parallel with the I/O circuitry for protecting the IC chip from an ESD event on the I/O pad. The FET also is coupled to a first voltage terminal of the I/O circuitry for providing a shunting path for the ESD event, thereby effectuating the protecting of the IC chip from the ESD event on the I/O pad. A first control circuit is coupled to a gate of the FET for maintaining the gate at a voltage level below a threshold voltage of the FET, thereby maintaining the FET in an off state during normal operation of the IC chip. Preferably a second control circuit is coupled between the FET and the first voltage terminal and operates in conjunction with the first control circuit for maintaining the FET in an off state during normal operation of the IC chip. The first control circuit preferably comprises a short circuit between the gate of the FET and the first voltage terminal, an inverter coupled between the gate of the FET and a second voltage terminal or a negative bias generator coupled to the gate of the FET. The second control circuit preferably comprises a short circuit between the FET and the first voltage terminal or a diode coupled between the FET and the first voltage terminal.

摘要翻译： 为具有耦合到I / O焊盘的I / O焊盘和I / O电路的IC芯片提供ESD保护方法和装置。 低阈值电压FET与I / O电路并联耦合到I / O焊盘，以保护IC芯片免受I / O焊盘上的ESD事件。 FET还耦合到I / O电路的第一电压端子，用于为ESD事件提供分流路径，从而实现IC芯片免受I / O焊盘上的ESD事件的保护。 第一控制电路耦合到FET的栅极，用于将栅极保持在低于FET阈值电压的电压电平，从而在IC芯片正常工作期间保持FET处于截止状态。 优选地，第二控制电路耦合在FET和第一电压端子之间，并且与第一控制电路一起操作，以在IC芯片的正常操作期间将FET保持在截止状态。 第一控制电路优选地包括在FET的栅极和第一电压端子之间的短路，耦合在FET的栅极和耦合到FET的栅极的第二电压端子或负偏压发生器之间的反相器。 第二控制电路优选地包括FET和第一电压端子之间的短路或耦合在FET和第一电压端子之间的二极管。

公开(公告)号：US6054745A

公开(公告)日：2000-04-25

申请号：US225071

申请日：1999-01-04

申请人： James S. Nakos ,  Richard Q. Williams

发明人： James S. Nakos ,  Richard Q. Williams

IPC分类号： B81B3/00 ,  H01H59/00 ,  H01L27/105 ,  H01L29/72

CPC分类号： H01L27/105 ,  H01H59/0009

摘要： A nonvolatile memory cell comprises a conductive cantilever beam having a free end in a first charge state, a first FET having a conductive gate in a second charge state and a pull-in electrode adapted to bring the cantilever beam into electrical contact with the gate to effect a charge state change in the gate. A pull-in electrode input is connected to the electrode, a cantilever input is connected to the cantilever, a column select input is connected to the first FET and a row select input is connected to the first FET. The nonvolatile memory cell is selected by signals applied to the row select input and the column select input. The cell also includes a second FET connected between the cantilever beam and the cantilever input for controlling the passage of signals from the cantilever input to the cantilever beam and a third FET connected between the pull-in electrode and the pull-in electrode input for controlling the passage of signals from the pull-in electrode input to the electrode. The second FET and third FET have gates connected to the row select input. The row select input turns on the second FET and the third FET to allow the passage of signals from the pull-in electrode input to the pull-in electrode and from the cantilever input to the cantilever beam when the nonvolatile memory cell is selected.

摘要翻译： 非易失性存储单元包括具有处于第一充电状态的自由端的导电悬臂梁，具有第二充电状态的导电栅极的第一FET和适于使悬臂梁与栅极电接触的引入电极 影响门的充电状态变化。 一个引入电极的输入端与电极连接，一个悬臂输入连接到悬臂上，一个列选择输入端连接到第一个FET，一个行选择输入端连接到第一个FET。 通过施加到行选择输入和列选择输入的信号来选择非易失性存储单元。 电池还包括连接在悬臂梁和悬臂输入端之间的第二FET，用于控制从悬臂输入到悬臂梁的信号通过;以及连接在引入电极和引入电极输入端之间的第三FET，用于控制 信号从拉入电极输入到电极的通过。 第二FET和第三FET具有连接到行选择输入的栅极。 当选择非易失性存储单元时，行选择输入打开第二FET和第三FET以允许从拉入电极输入到拉入电极的信号以及从悬臂输入到悬臂梁的信号。

公开(公告)号：US08745571B2

公开(公告)日：2014-06-03

申请号：US13026451

申请日：2011-02-14

申请人： Hongmei Li ,  Richard Q. Williams

发明人： Hongmei Li ,  Richard Q. Williams

IPC分类号： G06F15/04

CPC分类号： G06F17/5018 ,  G06F17/5068

摘要： The disclosure relates to the analysis of compensated layout shapes. A method in accordance with an embodiment includes: analyzing a semiconductor layout using a bucket structure, the layout including a semiconductor device; and applying a pattern template to a content of the bucket structure to identify a shape adjacent to the semiconductor device; wherein the pattern template is derived from layout groundrules.

摘要翻译： 本公开涉及补偿布局形状的分析。 根据实施例的方法包括：使用铲斗结构分析半导体布局，所述布局包括半导体器件; 以及将图案模板应用到所述桶结构的内容以识别与所述半导体器件相邻的形状; 其中，图案模板是从布局基本原理中导出的。

公开(公告)号：US20100050138A1

公开(公告)日：2010-02-25

申请号：US12196471

申请日：2008-08-22

申请人： Dureseti Chidambarrao ,  Tong Li ,  Richard Q. Williams ,  David W. Winston

发明人： Dureseti Chidambarrao ,  Tong Li ,  Richard Q. Williams ,  David W. Winston

IPC分类号： G06F17/50

CPC分类号： G06F17/5081 ,  G06F2217/12 ,  Y02P90/265

摘要： A layout of a semiconductor circuit is analyzed to calculate layout-dependant parameters that can include a mobility shift and a threshold voltage shift. Layout-dependant effects that affect the layout dependant parameters may include stress effects, rapid thermal anneal (RTA) effects, and lithographic effects. Intrinsic functions that do not reflect the layout-dependant effects are calculated, followed by calculation of scaling modifiers based on the layout-dependant parameters. A model output function that reflects the layout-dependant effects is obtained by multiplication of each of the intrinsic functions with a corresponding scaling parameter.

摘要翻译： 分析半导体电路的布局以计算可以包括迁移率偏移和阈值电压偏移的依赖于布局的参数。 影响依赖于布局的参数的依赖于布局的效应可能包括应力影响，快速热退火（RTA）效应和平版印刷效应。 计算不反映与布局有关的影响的内在函数，然后根据与布局相关的参数计算缩放修正符号。 通过将每个内在函数与相应的缩放参数相乘来获得反映与布局相关的效应的模型输出函数。

公开(公告)号：US20090179193A1

公开(公告)日：2009-07-16

申请号：US11972669

申请日：2008-01-11

申请人： Joerg Appenzeller ,  AJ Kleinosowski ,  Edward J. Nowak ,  Richard Q. Williams

发明人： Joerg Appenzeller ,  AJ Kleinosowski ,  Edward J. Nowak ,  Richard Q. Williams

IPC分类号： H01L27/092 ,  H01L21/8238

CPC分类号： H01L51/0541 ,  B82Y10/00 ,  H01L27/11 ,  H01L27/1104 ,  H01L27/283 ,  H01L51/0048 ,  H01L51/0558 ,  Y10S977/742 ,  Y10S977/75 ,  Y10S977/751 ,  Y10S977/752

摘要： Gate electrodes are formed on a semiconducting carbon nanotube, followed by deposition and patterning of a hole-inducing material layer and an electron inducing material layer on the carbon nanotube according to the pattern of a one dimensional circuit layout. Electrical isolation may be provided by cutting a portion of the carbon nanotube, forming a reverse biased junction of a hole-induced region and an electron-induced region of the carbon nanotube, or electrically biasing a region through a dielectric layer between two device regions of the carbon nanotube. The carbon nanotubes may be arranged such that hole-inducing material layer and electron-inducing material layer may be assigned to each carbon nanotube to form periodic structures such as a static random access memory (SRAM) array.

摘要翻译： 在半导体碳纳米管上形成栅电极，然后根据一维电路布局的图案在碳纳米管上沉积和图案化空穴诱导材料层和电子诱导材料层。 可以通过切割碳纳米管的一部分来形成电气隔离，形成空穴诱导区域和碳纳米管的电子诱导区域的反向偏置接合点，或者通过介电层在两个器件区域之间电气偏置区域 碳纳米管。 碳纳米管可以被布置为使得可以将空穴诱导材料层和电子诱导材料层分配给每个碳纳米管以形成诸如静态随机存取存储器（SRAM）阵列的周期性结构。

公开(公告)号：US07538391B2

公开(公告)日：2009-05-26

申请号：US11621228

申请日：2007-01-09

申请人： Dureseti Chidambarrao ,  Shreesh Narasimha ,  Edward J. Nowak ,  John J. Pekarik ,  Jeffrey W. Sleight ,  Richard Q. Williams

发明人： Dureseti Chidambarrao ,  Shreesh Narasimha ,  Edward J. Nowak ,  John J. Pekarik ,  Jeffrey W. Sleight ,  Richard Q. Williams

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/785 ,  H01L29/0649 ,  H01L29/66795 ,  H01L29/7843

摘要： A method of forming a transistor patterns a semiconductor fin on a substrate, such that the fin extends from the substrate. Then, the method forms a gate conductor over a central portion of the fin, leaving end portions of the fin exposed. Next, the end portions of the fin are doped with at least one impurity to leave the central portion of the fin as a semiconductor and form the end portions of the fin as conductors. The end portions of the fin are undercut to disconnect the end portions of the fin from the substrate, such that the fin is connected to the substrate along a central portion and is disconnected from the substrate along the end portions and that the end portions are free to move and the central portion is not free to move. A straining layer is formed on a first side of the fin and the straining layer imparts physical pressure on the fin such that the end portions are permanently moved away from a straight-line orientation with the central portion after the forming of the straining layer. Thus, the undercutting in combination with the forming of the straining layer curves the fin such that, when viewed from a top of the substrate, the fin is bowed and has a curved shape.

摘要翻译： 一种形成晶体管的方法在衬底上形成半导体鳍片，使得鳍片从衬底延伸。 然后，该方法在鳍片的中心部分上形成栅极导体，使翅片的端部部分露出。 接下来，翅片的端部掺杂有至少一种杂质，以使翅片的中心部分作为半导体，并将翅片的端部形成为导体。 翅片的端部被底切以使翅片的端部与基板断开，使得翅片沿着中心部分连接到基板，并且沿着端部与基板断开，并且端部部分是自由的 移动，中央部分不能自由移动。 在翅片的第一侧上形成有应变层，并且应变层在翅片上施加物理压力，使得端部在紧固层形成之后永久地与中心部分的直线取向远离。 因此，与形成应变层相结合的底切使翅片弯曲，使得当从基板的顶部观察时，翅片弯曲并具有弯曲形状。

公开(公告)号：US07462916B2

公开(公告)日：2008-12-09

申请号：US11458461

申请日：2006-07-19

申请人： Richard Q. Williams ,  Dureseti Chidambarrao ,  John J. Ellis-Monaghan ,  Shreesh Narasimha ,  Edward J. Nowak ,  John J. Pekarik

发明人： Richard Q. Williams ,  Dureseti Chidambarrao ,  John J. Ellis-Monaghan ,  Shreesh Narasimha ,  Edward J. Nowak ,  John J. Pekarik

IPC分类号： H01L29/76

CPC分类号： H01L29/78 ,  H01L21/7624 ,  H01L21/823807 ,  H01L29/66795 ,  H01L29/7846 ,  H01L29/7848 ,  H01L29/785

摘要： A FET structure is provided in which at least one stressor element provided at or near one corner of an active semiconductor region applies a stress in a first direction to one side of a channel region of the FET to apply a torsional stress to the channel region of the FET. In a particular embodiment, a second stressor element is provided at or near an opposite corner of the active semiconductor region to apply a stress in a second direction to an opposite side of a channel region of the FET, the second direction being opposite to the first direction. In this way, the first and second stressor elements cooperate together in applying a torsional stress to the channel region of the FET.

摘要翻译： 提供了一种FET结构，其中设置在有源半导体区域的一个角附近或附近的至少一个应激元件将第一方向上的应力施加到FET的沟道区域的一侧，以向该沟道区域的沟道区域施加扭转应力 FET。 在特定实施例中，第二应力元件设置在有源半导体区域的相对拐角处或附近，以将第二方向上的应力施加到FET的沟道区域的相对侧，第二方向与第一方向相反 方向。 以这种方式，第一和第二应激元件协同工作，将扭曲应力施加到FET的沟道区域。