公开(公告)号：US5629898A

公开(公告)日：1997-05-13

申请号：US607977

申请日：1996-02-29

申请人： Youji Idei ,  Katsuhiro Shimohigashi ,  Masakazu Aoki ,  Hiromasa Noda ,  Katsuyuki Sato ,  Hidetoshi Iwai ,  Makoto Saeki ,  Jun Murata ,  Yoshitaka Tadaki ,  Toshihiro Sekiguchi ,  Osamu Tsuchiya

发明人： Youji Idei ,  Katsuhiro Shimohigashi ,  Masakazu Aoki ,  Hiromasa Noda ,  Katsuyuki Sato ,  Hidetoshi Iwai ,  Makoto Saeki ,  Jun Murata ,  Yoshitaka Tadaki ,  Toshihiro Sekiguchi ,  Osamu Tsuchiya

IPC分类号： G11C11/406 ,  G11C11/407 ,  G11C7/00

CPC分类号： G11C11/406 ,  G11C2211/4016 ,  G11C2211/4061

摘要： A period pulse corresponding to the shortest information retention time of those of dynamic memory cells is counted to form a refresh address to be assigned to a plurality of word lines. A carry signal outputted from the refresh address counter is divided by a divider. For each of said plurality of word lines assigned with the refresh address, one of a short period corresponding to an output pulse of a timer or a long period corresponding to the divided pulse from the divider is stored in a storage circuit as refresh time setting information. A memory cell refresh operation to be performed by the refresh address is made valid or invalid for each word line according to the refresh time setting information stored in the storage circuit and the refresh time setting information itself is made invalid by the output pulse of the divider.

摘要翻译： 对与动态存储单元的最短信息保持时间对应的周期脉冲进行计数，以形成分配给多个字线的刷新地址。 从刷新地址计数器输出的进位信号由分频器分频。 对于分配有刷新地址的所述多个字线中的每一个，对应于定时器的输出脉冲的短周期中的一个或与来自分频器的分频脉冲相对应的长周期中的一个作为刷新时间设置信息被存储在存储电路中 。 根据存储在存储电路中的刷新时间设定信息，由刷新地址执行的存储器单元刷新动作对每个字线进行有效或无效，并且刷新时间设定信息本身被分频器的输出脉冲无效 。

公开(公告)号：US5504029A

公开(公告)日：1996-04-02

申请号：US254562

申请日：1994-06-06

申请人： Jun Murata ,  Yoshitaka Tadaki ,  Isamu Asano ,  Mitsuaki Horiuchi ,  Jun Sugiura ,  Hiroko Kaneko ,  Shinji Shimizu ,  Atsushi Hiraiwa ,  Hidetsugu Ogishi ,  Masakazu Sagawa ,  Masami Ozawa ,  Toshihiro Sekiguchi

发明人： Jun Murata ,  Yoshitaka Tadaki ,  Isamu Asano ,  Mitsuaki Horiuchi ,  Jun Sugiura ,  Hiroko Kaneko ,  Shinji Shimizu ,  Atsushi Hiraiwa ,  Hidetsugu Ogishi ,  Masakazu Sagawa ,  Masami Ozawa ,  Toshihiro Sekiguchi

IPC分类号： H01L27/10 ,  H01L21/8242 ,  H01L27/105 ,  H01L27/108 ,  H01L21/70 ,  H01L27/00

CPC分类号： H01L27/105 ,  H01L27/10808

摘要： A semiconductor integrated circuit device having a switching MISFET, and a capacitor element formed over the semiconductor substrate, is disclosed. The impurity concentration of the semiconductor region of the switching MISFET to which the capacitor element is connected is less than the impurity concentration of semiconductor regions of MISFETs of peripheral circuitry. The Y-select signal line overlaps the lower electrode layer of the capacitor element. A potential barrier layer, provided at least under the semiconductor region of the switching MISFET to which the capacitor element is connected, is formed by diffusion of an impurity for a channel stopper region. The dielectric film of the capacitor element is co-extensive with the capacitor electrode layer over it. The capacitor dielectric film is a silicon nitride film having a silicon oxide layer thereon, the silicon oxide layer being formed by oxidizing a surface layer of the silicon nitride under high pressure. An aluminum wiring layer and a protective (and/or barrier) layer are formed by sputtering in the same vacuum sputtering chamber without breaking the vacuum between forming the layers; and a refractory metal, or a refractory metal silicide QSi.sub.x, where Q is a refractory metal and x is between 0 and 2, is used as a protective layer, for an aluminum wiring containing an added element (e.g., Cu) to prevent migration.

摘要翻译： 公开了一种具有开关MISFET的半导体集成电路器件和形成在半导体衬底上的电容器元件。 电容器元件连接的开关MISFET的半导体区域的杂质浓度小于外围电路的MISFET的半导体区域的杂质浓度。 Y选择信号线与电容器元件的下电极层重叠。 至少在与电容器元件连接的开关MISFET的半导体区域下方设置的势垒层通过用于沟道阻挡区域的杂质的扩散而形成。 电容器元件的电介质膜与其上的电容器电极层共同扩展。 电容器电介质膜是其上具有氧化硅层的氮化硅膜，氧化硅层通过在高压下氧化氮化硅的表面层而形成。 通过溅射在相同的真空溅射室中形成铝布线层和保护（和/或阻挡层），而不破坏形成层之间的真空; 和难熔金属或难熔金属硅化物QSix，其中Q是难熔金属，x在0和2之间，用作含有添加元素（例如Cu）以防止迁移的铝布线的保护层。

公开(公告)号：US20060024875A1

公开(公告)日：2006-02-02

申请号：US11234118

申请日：2005-09-26

申请人： Makoto Yoshida ,  Takahiro Kumauchi ,  Yoshitaka Tadaki ,  Kazuhiko Kajigaya ,  Hideo Aoki ,  Isamu Asano

发明人： Makoto Yoshida ,  Takahiro Kumauchi ,  Yoshitaka Tadaki ,  Kazuhiko Kajigaya ,  Hideo Aoki ,  Isamu Asano

IPC分类号： H01L21/8234

CPC分类号： H01L21/2652 ,  H01L21/32051 ,  H01L21/32053 ,  H01L21/324 ,  H01L21/76802 ,  H01L21/76849 ,  H01L21/76855 ,  H01L21/76889 ,  H01L21/76897 ,  H01L21/823814 ,  H01L21/823871 ,  H01L23/53257 ,  H01L27/1052 ,  H01L27/10814 ,  H01L27/10855 ,  H01L27/10873 ,  H01L27/10882 ,  H01L27/10894 ,  H01L29/6659 ,  H01L2924/0002 ,  H01L2924/00

摘要： In a process for manufacturing a semiconductor integrated circuit device having a MISFET, in order that a shallow junction between the source/drain of the MISFET and a semiconductor substrate may be realized by reducing the number of heat treatment steps, all conductive films to be deposited on the semiconductor substrate are deposited at a temperature of 500° C. or lower at a step after the MISFET has been formed. Moreover, all insulating films to be deposited over the semiconductor substrate are deposited at a temperature of 500° C. or lower at a step after the MISFET has been formed.

摘要翻译： 在制造具有MISFET的半导体集成电路器件的工艺中，为了通过减少热处理步骤的数量来实现MISFET的源极/漏极与半导体衬底之间的浅结，可以将所有导电膜沉积 在形成MISFET之后的步骤中，在500℃以下的温度下沉积半导体基板。 此外，要沉积在半导体衬底上的所有绝缘膜在形成MISFET之后的步骤中在500℃或更低的温度下沉积。

公开(公告)号：US5981369A

公开(公告)日：1999-11-09

申请号：US865864

申请日：1997-05-30

申请人： Makoto Yoshida ,  Takahiro Kumauchi ,  Yoshitaka Tadaki ,  Kazuhiko Kajigaya ,  Hideo Aoki ,  Isamu Asano

发明人： Makoto Yoshida ,  Takahiro Kumauchi ,  Yoshitaka Tadaki ,  Kazuhiko Kajigaya ,  Hideo Aoki ,  Isamu Asano

IPC分类号： H01L21/28 ,  H01L21/3205 ,  H01L21/60 ,  H01L21/768 ,  H01L21/8238 ,  H01L21/8242 ,  H01L23/52 ,  H01L27/092 ,  H01L27/10 ,  H01L27/108 ,  H01L21/44

CPC分类号： H01L21/823871 ,  H01L21/76877 ,  H01L21/76897 ,  H01L21/823814 ,  H01L21/76849 ,  H01L21/76853 ,  H01L27/10855 ,  H01L27/10894

摘要： In a process for manufacturing a semiconductor integrated circuit device having a MISFET, in order that a shallow junction between the source/drain of the MISFET and a semiconductor substrate may be realized by reducing the number of heat treatment steps, all conductive films to be deposited on the semiconductor substrate are deposited at a temperature of 500.degree. C. or lower at a step after the MISFET has been formed. Moreover, all insulating films to be deposited over the semiconductor substrate are deposited at a temperature of 500.degree. C. or lower at a step after the MISFET has been formed.

摘要翻译： 在制造具有MISFET的半导体集成电路器件的工艺中，为了通过减少热处理步骤的数量来实现MISFET的源极/漏极与半导体衬底之间的浅结，可以将所有导电膜沉积 在形成MISFET之后的步骤中，在半导体基板上淀积5​​00℃以下的温度。 此外，要沉积在半导体衬底上的所有绝缘膜在形成MISFET之后的步骤中在500℃或更低的温度下沉积。

公开(公告)号：US20050042822A1

公开(公告)日：2005-02-24

申请号：US10950595

申请日：2004-09-28

申请人： Makoto Yoshida ,  Takahiro Kumauchi ,  Yoshitaka Tadaki ,  Kazuhiko Kajigaya ,  Hideo Aoki ,  Isamu Asano

发明人： Makoto Yoshida ,  Takahiro Kumauchi ,  Yoshitaka Tadaki ,  Kazuhiko Kajigaya ,  Hideo Aoki ,  Isamu Asano

IPC分类号： H01L21/265 ,  H01L21/3205 ,  H01L21/324 ,  H01L21/336 ,  H01L21/60 ,  H01L21/768 ,  H01L21/8238 ,  H01L21/8239 ,  H01L21/8242 ,  H01L27/108 ,  H01L21/8249 ,  H01L21/8234

CPC分类号： H01L21/2652 ,  H01L21/32051 ,  H01L21/32053 ,  H01L21/324 ,  H01L21/76802 ,  H01L21/76849 ,  H01L21/76855 ,  H01L21/76889 ,  H01L21/76897 ,  H01L21/823814 ,  H01L21/823871 ,  H01L23/53257 ,  H01L27/1052 ,  H01L27/10814 ,  H01L27/10855 ,  H01L27/10873 ,  H01L27/10882 ,  H01L27/10894 ,  H01L29/6659 ,  H01L2924/0002 ,  H01L2924/00

摘要： In a process for manufacturing a semiconductor integrated circuit device having a MISFET, in order that a shallow junction between the source/drain of the MISFET and a semiconductor substrate may be realized by reducing the number of heat treatment steps, all conductive films to be deposited on the semiconductor substrate are deposited at a temperature of 500° C. or lower at a step after the MISFET has been formed. Moreover, all insulating films to be deposited over the semiconductor substrate are deposited at a temperature of 500° C. or lower at a step after the MISFET has been formed.

摘要翻译： 在制造具有MISFET的半导体集成电路器件的工艺中，为了通过减少热处理步骤的数量来实现MISFET的源极/漏极与半导体衬底之间的浅结，可以将所有导电膜沉积 在形成MISFET之后的步骤中，在500℃以下的温度下沉积半导体基板。 此外，要沉积在半导体衬底上的所有绝缘膜在形成MISFET之后的步骤中在500℃或更低的温度下沉积。

公开(公告)号：US06815762B2

公开(公告)日：2004-11-09

申请号：US09416959

申请日：1999-10-13

申请人： Makoto Yoshida ,  Takahiro Kumauchi ,  Yoshitaka Tadaki ,  Kazuhiko Kajigaya ,  Hideo Aoki ,  Isamu Asano

发明人： Makoto Yoshida ,  Takahiro Kumauchi ,  Yoshitaka Tadaki ,  Kazuhiko Kajigaya ,  Hideo Aoki ,  Isamu Asano

IPC分类号： H01L29788

CPC分类号： H01L21/76897 ,  H01L21/2652 ,  H01L21/32051 ,  H01L21/32053 ,  H01L21/324 ,  H01L21/76802 ,  H01L21/76849 ,  H01L21/76855 ,  H01L21/76889 ,  H01L21/823814 ,  H01L21/823871 ,  H01L23/53257 ,  H01L27/1052 ,  H01L27/10814 ,  H01L27/10855 ,  H01L27/10873 ,  H01L27/10882 ,  H01L27/10894 ,  H01L29/6659 ,  H01L2924/0002 ,  H01L2924/00

摘要： In a process for manufacturing a semiconductor integrated circuit device having a MISFET, in order that a shallow junction between the source/drain of the MISFET and a semiconductor substrate may be realized by reducing the number of heat treatment steps, all conductive films to be deposited on the semiconductor substrate are deposited at a temperature of 500° C. or lower at a step after the MISFET has been formed. Moreover, all insulating films to be deposited over the semiconductor substrate are deposited at a temperature of 500° C. or lower at a step after the MISFET has been formed.

摘要翻译： 在制造具有MISFET的半导体集成电路器件的工艺中，为了通过减少热处理步骤的数量来实现MISFET的源极/漏极与半导体衬底之间的浅结，可以将所有导电膜沉积 在形成MISFET之后的步骤中，在500℃以下的温度下沉积半导体基板。 此外，要沉积在半导体衬底上的所有绝缘膜在形成MISFET之后的步骤中在500℃或更低的温度下沉积。

公开(公告)号：US06674112B1

公开(公告)日：2004-01-06

申请号：US09446509

申请日：1999-12-27

申请人： Yoshitaka Tadaki ,  Yutaka Ito

发明人： Yoshitaka Tadaki ,  Yutaka Ito

IPC分类号： H01L27108

CPC分类号： H01L27/105 ,  G11C11/4076 ,  G11C11/4097 ,  H01L27/0214 ,  H01L27/10897

摘要： A semiconductor integrated circuit device has a semiconductor substrate and operates when supplied with appositive supply voltage and a circuit ground potential. The device has word lines, pairs of bit lines, data storage capacitors, and N-channel MOSFETs each having a gate connected to any one of the word lines and a source-drain path interposed between one of the paired bit lines on the one hand and a terminal of any one of the data storage capacitors on the other hand. A positive internal voltage higher than a circuit ground potential is generated and fed as a bias voltage to P-type regions wherein address selection MOSFETs of dynamic memory cells are formed.

摘要翻译： 半导体集成电路器件具有半导体衬底，并在被供给正电源电压和电路接地电位时工作。 该器件具有字线，成对的位线，数据存储电容器和N沟道MOSFET，其各自具有连接到任何一条字线的栅极和一方面插入在一对位线之一中的源极 - 漏极通路 和任何一个数据存储电容器的端子。 产生高于电路接地电位的正内部电压，并将其作为偏置电压馈送到形成动态存储单元的地址选择MOSFET的P型区域。

公开(公告)号：US08754489B2

公开(公告)日：2014-06-17

申请号：US13605340

申请日：2012-09-06

申请人： Shuntaro Machida ,  Hiroyuki Enomoto ,  Yoshitaka Tadaki

发明人： Shuntaro Machida ,  Hiroyuki Enomoto ,  Yoshitaka Tadaki

IPC分类号： H01L27/14

CPC分类号： B06B1/0292 ,  Y10T29/49005

摘要： An ultrasonic transducer includes a first electrode, a first insulation film covering the first electrode, a hollow part overlapping the first electrode on the first insulation film, a second insulation film covering the hollow part, a second electrode overlapping the hollow part on the second insulation film, and an interconnection joined to the second electrode. An edge of the first electrode is formed so as to moderate a step of the first electrode.

摘要翻译： 超声波换能器包括第一电极，覆盖第一电极的第一绝缘膜，与第一绝缘膜上的第一电极重叠的中空部分，覆盖中空部分的第二绝缘膜，与第二绝缘体上的中空部分重叠的第二电极 膜，以及与第二电极接合的互连。 形成第一电极的边缘以调节第一电极的台阶。

公开(公告)号：US20100148594A1

公开(公告)日：2010-06-17

申请号：US12714631

申请日：2010-03-01

申请人： Shuntaro Machida ,  Hiroyuki Enomoto ,  Yoshitaka Tadaki ,  Tatsuya Nagata

发明人： Shuntaro Machida ,  Hiroyuki Enomoto ,  Yoshitaka Tadaki ,  Tatsuya Nagata

IPC分类号： H02N11/00

CPC分类号： B06B1/0292

摘要： An ultrasonic transducer includes a first electrode, a second electrode, an insulating film disposed between the first and second electrodes, and a cavity disposed between the first and second electrodes. The insulating film includes a projection extending in the cavity, and a portion of the cavity is disposed between the projection and the first electrode. A portion of one of the first electrode and the second electrode has an opening corresponding to a position of the projection of the insulating film when viewed in plan view.

摘要翻译： 超声换能器包括第一电极，第二电极，设置在第一和第二电极之间的绝缘膜，以及设置在第一和第二电极之间的空腔。 绝缘膜包括在空腔中延伸的突起，并且空腔的一部分设置在突起和第一电极之间。 当在平面图中观察时，第一电极和第二电极中的一个的一部分具有对应于绝缘膜的突起的位置的开口。

公开(公告)号：US20080042225A1

公开(公告)日：2008-02-21

申请号：US11671040

申请日：2007-02-05

申请人： Shuntaro Machida ,  Hiroyuki Enomoto ,  Yoshitaka Tadaki

发明人： Shuntaro Machida ,  Hiroyuki Enomoto ,  Yoshitaka Tadaki

IPC分类号： H01L29/84 ,  H01L21/62

CPC分类号： B06B1/0292 ,  Y10T29/49005

摘要： This invention provides a technique whereby, even if a step is produced by splitting a lower electrode into component elements, resistance increase of an upper electrode, damage to a membrane and decrease of dielectric strength between an upper electrode and the lower electrode, are reduced. In an ultrasonic transducer comprising plural lower electrodes, an insulation film covering the lower electrodes, plural hollow parts formed to overlap the lower electrodes on the insulation film, an insulation film filling the gaps among the hollow parts, an insulation film covering the hollow parts and insulation film, plural upper electrodes formed to overlap the hollow parts on the insulation film and plural interconnections joining them, the surfaces of the hollow parts and insulation film are flattened to the same height.

摘要翻译： 本发明提供一种技术，即使通过将下部电极分割成成分元件而产生台阶，也能够降低上部电极的电阻增加，膜的损伤以及上部电极与下部电极之间的介电强度的降低。 在包括多个下电极的超声波换能器中，覆盖下电极的绝缘膜，形成为与绝缘膜上的下电极重叠的多个中空部，填充中空部之间的间隙的绝缘膜，覆盖中空部的绝缘膜， 绝缘膜，形成为与绝缘膜上的中空部分重叠的多个上电极和连接它们的多个互连，中空部分和绝缘膜的表面被平坦化到相同的高度。