公开(公告)号：US08420462B2

公开(公告)日：2013-04-16

申请号：US12842067

申请日：2010-07-23

申请人： Satoshi Kobayashi ,  Ikuko Kawamata

发明人： Satoshi Kobayashi ,  Ikuko Kawamata

IPC分类号： H01L21/00

CPC分类号： H01L29/78696 ,  H01L29/04 ,  H01L29/41733 ,  H01L29/4908 ,  H01L29/66765

摘要： A display device including a thin film transistor with high electric characteristics and high reliability, and a method for manufacturing the display device in high yield are proposed. In a display device including a channel stop thin film transistor with an inverted-staggered structure, the channel stop thin film transistor with the inverted-staggered structure includes a microcrystalline semiconductor film including a channel formation region. An impurity region including an impurity element imparting one conductivity type is formed as selected in a region in the channel formation region of the microcrystalline semiconductor film which does not overlap with a source electrode or a drain electrode. In the channel formation region, a non-doped region, to which the impurity element imparting one conductivity type is not added, is formed between the impurity region, which is a doped region to which the impurity element is added, and the source region or the drain region.

摘要翻译： 提出一种包括具有高电特性和高可靠性的薄膜晶体管的显示装置，以及用于以高产量制造显示装置的方法。 在具有反交错结构的通道阻挡薄膜晶体管的显示装置中，具有反交错结构的通道阻挡薄膜晶体管包括包括沟道形成区域的微晶半导体膜。 在微结晶半导体膜的沟道形成区域中，与源电极或漏电极不重叠的区域中选择包含赋予一种导电类型的杂质元素的杂质区域。 在沟道形成区域中，在作为添加了杂质元素的掺杂区域的杂质区域与源极区域之间形成有不添加赋予一种导电型的杂质元素的非掺杂区域，或 漏极区域。

公开(公告)号：US08232598B2

公开(公告)日：2012-07-31

申请号：US12232311

申请日：2008-09-15

申请人： Shunpei Yamazaki ,  Ikuko Kawamata ,  Atsushi Miyaguchi

发明人： Shunpei Yamazaki ,  Ikuko Kawamata ,  Atsushi Miyaguchi

IPC分类号： H01L27/12

CPC分类号： H01L21/67144 ,  H01L21/76254 ,  H01L21/8221 ,  H01L27/0688 ,  H01L27/1203 ,  H01L27/124 ,  H01L27/3262 ,  H01L29/66772 ,  H01L2227/326 ,  H01L2924/00011 ,  H01L2224/80001

摘要： To provide a display device which can realize high performance of a field-effect transistor which forms a pixel of the display device and which can achieve improvement in an aperture ratio of a pixel, which has been reduced due to increase in the number of field-effect transistors, and reduction in the area of the field-effect transistor which occupies the pixel, without depending on a microfabrication technique of the field-effect transistor, even when the number of field-effect transistors in the pixel is increased. A display device is provided with a plurality of pixels in which a plurality of field-effect transistors including a semiconductor layer which is separated from a semiconductor substrate and is bonded to a supporting substrate having an insulating surface are stacked with a planarization layer interposed therebetween.

摘要翻译： 为了提供能够实现形成显示装置的像素的场效应晶体管的高性能的显示装置，其可以实现由于场效应晶体管的数量的增加而减小的像素的开口率的提高， 效应晶体管，并且即使当像素中的场效应晶体管的数量增加时，占据像素的场效应晶体管的面积减小，而不依赖于场效应晶体管的微细加工技术。 显示装置设置有多个像素，其中包括与半导体衬底分离并且与具有绝缘表面的支撑衬底结合的半导体层的多个场效应晶体管之间插入有平坦化层。

公开(公告)号：US20100289026A1

公开(公告)日：2010-11-18

申请号：US12844072

申请日：2010-07-27

申请人： Shunpei Yamazaki ,  Hironobu Shoji ,  Ikuko Kawamata

发明人： Shunpei Yamazaki ,  Hironobu Shoji ,  Ikuko Kawamata

IPC分类号： H01L33/00

CPC分类号： H01L21/76801 ,  H01L21/288 ,  H01L21/76838 ,  H01L27/124 ,  H01L27/1285 ,  H01L27/1292 ,  H01L2924/0002 ,  H01L2924/00

摘要： When a conductive layer is formed, a first liquid composition containing a conductive material is applied on an outer side of a pattern that is desired to be formed (corresponding to a contour or an edge portion of a pattern), and a first conductive layer (insulating layer) having a frame-shape is formed. A second liquid composition containing a conductive material is applied so as to fill a space inside the first conductive layer having a frame-shape, whereby a second conductive layer is formed. The first conductive layer and the second conductive layer are formed so as to be in contact with each other, and the first conductive layer is formed so as to surround the second conductive layer. Therefore, the first conductive layer and the second conductive layer can be used as one continuous conductive layer.

摘要翻译： 当形成导电层时，将含有导电材料的第一液体组合物施加在期望形成的图案的外侧（对应于图案的轮廓或边缘部分）和第一导电层（ 绝缘层）形成。 涂布含有导电材料的第二液体组合物，以填充具有框架形状的第一导电层内的空间，由此形成第二导电层。 第一导电层和第二导电层形成为彼此接触，并且第一导电层形成为围绕第二导电层。 因此，第一导电层和第二导电层可以用作一个连续导电层。

公开(公告)号：US20100120226A1

公开(公告)日：2010-05-13

申请号：US12692790

申请日：2010-01-25

申请人： Shunpei Yamazaki ,  Ikuko Kawamata ,  Yasuyuki Arai

发明人： Shunpei Yamazaki ,  Ikuko Kawamata ,  Yasuyuki Arai

IPC分类号： H01L21/762

CPC分类号： H01L21/76254 ,  G11C16/0416 ,  G11C16/0433 ,  G11C16/0483 ,  H01L21/84 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/1203

摘要： When single crystal semiconductor layers are transposed from a single crystal semiconductor substrate (a bond wafer), the single crystal semiconductor substrate is etched selectively (this step is also referred to as groove processing), and a plurality of single crystal semiconductor layers, which are being divided in size of manufactured semiconductor elements, are transposed to a different substrate (a base substrate). Thus, a plurality of island-shaped single crystal semiconductor layers (SOI layers) can be formed over the base substrate. Further, etching is performed on the single crystal semiconductor layers formed over the base substrate, and the shapes of the SOI layers are controlled precisely by being processed and modified.

公开(公告)号：US20080042288A1

公开(公告)日：2008-02-21

申请号：US11823095

申请日：2007-06-26

申请人： Shunpei Yamazaki ,  Hironobu Shoji ,  Ikuko Kawamata

发明人： Shunpei Yamazaki ,  Hironobu Shoji ,  Ikuko Kawamata

IPC分类号： H01L23/485 ,  H01L21/44

CPC分类号： H01L21/76801 ,  H01L21/288 ,  H01L21/76838 ,  H01L27/124 ,  H01L27/1285 ,  H01L27/1292 ,  H01L2924/0002 ,  H01L2924/00

摘要： When a conductive layer is formed, a first liquid composition containing a conductive material is applied on an outer side of a pattern that is desired to be formed (corresponding to a contour or an edge portion of a pattern), and a first conductive layer (insulating layer) having a frame-shape is formed. A second liquid composition containing a conductive material is applied so as to fill a space inside the first conductive layer having a frame-shape, whereby a second conductive layer is formed. The first conductive layer and the second conductive layer are formed so as to be in contact with each other, and the first conductive layer is formed so as to surround the second conductive layer. Therefore, the first conductive layer and the second conductive layer can be used as one continuous conductive layer.

摘要翻译： 当形成导电层时，将含有导电材料的第一液体组合物施加在期望形成的图案的外侧（对应于图案的轮廓或边缘部分）和第一导电层（ 绝缘层）形成。 涂布含有导电材料的第二液体组合物，以填充具有框架形状的第一导电层内的空间，由此形成第二导电层。 第一导电层和第二导电层形成为彼此接触，并且第一导电层形成为围绕第二导电层。 因此，第一导电层和第二导电层可以用作一个连续导电层。

公开(公告)号：US20060189047A1

公开(公告)日：2006-08-24

申请号：US11193513

申请日：2005-08-01

申请人： Shunpei Yamazaki ,  Shinji Maekawa ,  Tatsuya Honda ,  Hironobu Shoji ,  Osamu Nakamura ,  Yukie Suzuki ,  Ikuko Kawamata

发明人： Shunpei Yamazaki ,  Shinji Maekawa ,  Tatsuya Honda ,  Hironobu Shoji ,  Osamu Nakamura ,  Yukie Suzuki ,  Ikuko Kawamata

IPC分类号： H01L21/84

CPC分类号： H01L27/1277 ,  H01L27/1214 ,  H01L27/124 ,  H01L27/1251 ,  H01L27/1288

摘要： [Object] The invention provides a method of fabricating a semiconductor device having an inversely staggered TFT capable of high-speed operation, which has few variations of the threshold. In addition, the invention provides a method of fabricating a semiconductor device with high throughput where the cost reduction is achieved with few materials. [Means for Solving the Problem] According to the invention, a semiconductor device is fabricated by forming an inversely staggered TFT which is obtained by forming a gate electrode using a highly heat-resistant material, depositing an amorphous semiconductor film, adding a catalytic element into the amorphous semiconductor film and heating the amorphous semiconductor film to form a crystalline semiconductor film, forming a layer containing a donor element or a rare gas element over the crystalline semiconductor film and heating the layer to remove the catalytic element from the crystalline semiconductor film, forming a semiconductor region by utilizing a part of the crystalline semiconductor film, forming a source electrode and a drain electrode to be electrically connected to the semiconductor region, and forming a gate wiring to be connected to the gate electrode.

摘要翻译： 本发明提供了一种制造具有能够高速操作的反交错TFT的半导体器件的方法，其具有极小的阈值变化。 此外，本发明提供了一种制造具有高产量的半导体器件的方法，其中通过少量材料实现成本降低。 解决问题的手段根据本发明，通过形成逆交错TFT来制造半导体器件，该TFT是使用高耐热材料形成栅电极，沉积非晶半导体膜，将催化元素添加到 非晶半导体膜并加热非晶半导体膜以形成晶体半导体膜，在结晶半导体膜上形成包含施主元素或稀有气体元素的层，并加热该层从结晶半导体膜除去催化元素，形成 通过利用晶体半导体膜的一部分形成半导体区域，形成与半导体区域电连接的源电极和漏电极，以及形成与栅电极连接的栅极布线。

公开(公告)号：US08581260B2

公开(公告)日：2013-11-12

申请号：US12027815

申请日：2008-02-07

申请人： Shunpei Yamazaki ,  Ikuko Kawamata ,  Yasuyuki Arai

发明人： Shunpei Yamazaki ,  Ikuko Kawamata ,  Yasuyuki Arai

IPC分类号： H01L29/04

CPC分类号： H01L27/1233 ,  H01L27/105 ,  H01L27/11526 ,  H01L27/11534 ,  H01L27/11546 ,  H01L27/1203 ,  H01L27/1214 ,  H01L27/1237 ,  H01L29/66825 ,  H01L29/7881

摘要： Plural kinds of thin film transistors having different film thicknesses of semiconductor layers are provided over a substrate having an insulating surface. A channel formation region of semiconductor layer in a thin film transistor for which high speed operation is required is made thinner than a channel formation region of a semiconductor layer of a thin film transistor for which high withstand voltage is required. A gate insulating layer of the thin film transistor for which high speed operation is required may be thinner than a gate insulating layer of the thin film transistor for which high withstand voltage is required.

摘要翻译： 在具有绝缘表面的基板上设置具有不同膜厚的半导体层的多种薄膜晶体管。 要求高速运行的薄膜晶体管中的半导体层的沟道形成区域比需要高耐压的薄膜晶体管的半导体层的沟道形成区域薄。 需要高速运行的薄膜晶体管的栅极绝缘层可以比要求高耐压的薄膜晶体管的栅极绝缘层更薄。

公开(公告)号：US08427420B2

公开(公告)日：2013-04-23

申请号：US12769266

申请日：2010-04-28

申请人： Shunpei Yamazaki ,  Jun Koyama ,  Yasuyuki Arai ,  Ikuko Kawamata ,  Atsushi Miyaguchi ,  Yoshitaka Moriya

发明人： Shunpei Yamazaki ,  Jun Koyama ,  Yasuyuki Arai ,  Ikuko Kawamata ,  Atsushi Miyaguchi ,  Yoshitaka Moriya

IPC分类号： G09G3/34 ,  G09G3/36

CPC分类号： G06F1/1652 ,  G02F1/133305 ,  G02F1/13452 ,  G02F1/1368 ,  G06F1/1616 ,  G06F1/1635 ,  G06F1/1643 ,  G06F1/1647 ,  G06F3/1423 ,  G06F3/147 ,  G09G3/20 ,  G09G3/2096 ,  G09G3/3225 ,  G09G3/344 ,  G09G3/3648 ,  G09G5/003 ,  G09G2300/08 ,  G09G2310/0218 ,  G09G2310/0267 ,  G09G2310/0275 ,  G09G2310/0281 ,  G09G2330/02 ,  G09G2330/021 ,  G09G2360/144 ,  G09G2380/02 ,  G09G2380/14

摘要： An e-book reader in which destruction of a driver circuit at the time when a flexible panel is handled is inhibited. In addition, an e-book reader having a simplified structure. A plurality of flexible display panels each including a display portion in which display control is performed by a scan line driver circuit and a signal line driver circuit, and a binding portion fastening the plurality of display panels together are included. The signal line driver circuit is provided inside the binding portion, and the scan line driver circuit is provided at the edge of the display panel in a direction perpendicular to the binding portion.

公开(公告)号：US08048473B2

公开(公告)日：2011-11-01

申请号：US11823410

申请日：2007-06-27

申请人： Shunpei Yamazaki ,  Hironobu Shoji ,  Ikuko Kawamata

发明人： Shunpei Yamazaki ,  Hironobu Shoji ,  Ikuko Kawamata

IPC分类号： B05D5/08 ,  H01B13/00 ,  C23F1/00

CPC分类号： H01L27/1214 ,  H01L21/31105 ,  H01L27/124 ,  H01L27/1285 ,  H01L27/1288 ,  H01L27/1292 ,  Y02P80/30

摘要： When a mask layer is formed, a first liquid composition containing a mask-layer-forming material is applied on an outer side of a pattern that is desired to be formed (corresponding to a contour or an edge portion of a pattern) to form a first mask layer having a frame shape. A second liquid composition containing a mask-layer-forming material is applied so as to fill a space inside the first mask layer having a frame shape to form a second mask layer. The first mask layer and the second mask layer are formed to be in contact with each other, and the first mask layer is formed to surround the second mask layer. Therefore, the first mask layer and the second mask layer can be used as one continuous mask layer.

摘要翻译： 当形成掩模层时，将含有掩模层形成材料的第一液体组合物施加在期望形成的图案的外侧（对应于图案的轮廓或边缘部分），以形成 第一掩模层具有框架形状。 涂布含有掩模层形成材料的第二液体组合物，以填充具有框架形状的第一掩模层内的空间，以形成第二掩模层。 第一掩模层和第二掩模层形成为彼此接触，并且第一掩模层形成为围绕第二掩模层。 因此，第一掩模层和第二掩模层可以用作一个连续掩模层。

公开(公告)号：US07972935B2

公开(公告)日：2011-07-05

申请号：US12858525

申请日：2010-08-18

申请人： Shunpei Yamazaki ,  Ikuko Kawamata ,  Yasuyuki Arai

发明人： Shunpei Yamazaki ,  Ikuko Kawamata ,  Yasuyuki Arai

IPC分类号： H01L21/30

CPC分类号： H01L21/76254 ,  G11C16/0416 ,  G11C16/0433 ,  G11C16/0483 ,  H01L21/84 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/1203

摘要： When single crystal semiconductor layers are transposed from a single crystal semiconductor substrate (a bond wafer), the single crystal semiconductor substrate is etched selectively (this step is also referred to as groove processing), and a plurality of single crystal semiconductor layers, which are being divided in size of manufactured semiconductor elements, are transposed to a different substrate (a base substrate). Thus, a plurality of island-shaped single crystal semiconductor layers (SOI layers) can be formed over the base substrate. Further, etching is performed on the single crystal semiconductor layers formed over the base substrate, and the shapes of the SOI layers are controlled precisely by being processed and modified.

摘要翻译： 当单晶半导体层从单晶半导体衬底（接合晶片）转置时，选择性地蚀刻单晶半导体衬底（该步骤也称为沟槽处理），并且多个单晶半导体层是 被分割成制造的半导体元件的尺寸，被转置到不同的基板（基底）。 因此，可以在基底基板上形成多个岛状单晶半导体层（SOI层）。 此外，对形成在基底基板上的单晶半导体层进行蚀刻，并且通过加工和改进来精确地控制SOI层的形状。