公开(公告)号：US20220285437A1

公开(公告)日：2022-09-08

申请号：US17750386

申请日：2022-05-22

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ya-Huei Tsai ,  Rai-Min Huang ,  Yu-Ping Wang ,  Hung-Yueh Chen

IPC: H01L27/22 ,  H01L23/528 ,  H01L43/02

Abstract: A layout pattern for magnetoresistive random access memory (MRAM) includes a substrate having a first active region, a second active region, and a word line connecting region between the first active region and the second active region, a first gate pattern extending along a first direction from the first active region to the second active region, a second gate pattern extending along the first direction from the first active region to the second active region, a first magnetic tunneling junction (MTJ) between the first gate pattern and the second pattern and within the word line connecting region, and a second MTJ between the first gate pattern and the second gate pattern in the first active region. Preferably, top surfaces of the first MTJ and the second MTJ are coplanar.

公开(公告)号：US20220216397A1

公开(公告)日：2022-07-07

申请号：US17705404

申请日：2022-03-28

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hui-Lin Wang ,  Chia-Chang Hsu ,  Rai-Min Huang

IPC: H01L43/12 ,  H01L23/544 ,  H01L43/02 ,  H01L27/22

Abstract: A method for forming a semiconductor structure includes the steps of providing a substrate having a device region and an alignment mark region, forming a first dielectric layer on the substrate and a second dielectric layer on the first dielectric layer, forming a conductive via in the second dielectric layer on the device region, forming a mask layer on the second dielectric layer, etching the second dielectric layer and the first dielectric layer through an opening of the mask layer on the alignment mark region to form a first trench through the second dielectric layer and an upper portion of the first dielectric layer and a plurality of second trenches in the first dielectric layer directly under the first trench. Afterward, a memory stack structure is formed on the second dielectric layer, covering the conductive via and filling into the first trench and the second trenches.

公开(公告)号：US20210391531A1

公开(公告)日：2021-12-16

申请号：US16930291

申请日：2020-07-15

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Jia-Rong Wu ,  Rai-Min Huang ,  I-Fan Chang ,  Ya-Huei Tsai ,  Yu-Ping Wang

IPC: H01L43/02 ,  H01L43/12 ,  H01L27/22

Abstract: A method for fabricating a semiconductor device includes the steps of: forming a first inter-metal dielectric (IMD) layer on a substrate; forming a first patterned mask on the first IMD layer, in which the first patterned mask includes a first slot extending along a first direction; forming a second patterned mask on the first patterned mask, in which the second patterned mask includes a second slot extending along a second direction and the first slot intersects the second slot to form a third slot; and forming a first metal interconnection in the third slot.

公开(公告)号：US20210167282A1

公开(公告)日：2021-06-03

申请号：US17152703

申请日：2021-01-19

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hui-Lin Wang ,  Chia-Chang Hsu ,  Rai-Min Huang

IPC: H01L43/12 ,  H01L23/544 ,  H01L27/22 ,  H01L43/02

Abstract: A semiconductor structure is provided in the present invention, including a substrate having a device region and an alignment mark region defined thereon, a dielectric layer disposed on the substrate, a conductive via formed in the dielectric layer on the device region, a first trench formed in the dielectric layer on the alignment mark, a plurality of second trenches formed in the dielectric layer directly under the first trench and exposed from a bottom surface of the first trench, and a memory stacked structure disposed on the dielectric layer, directly covering a top surface of the conductive via and filling into the first trench and the second trench.

公开(公告)号：US20200212030A1

公开(公告)日：2020-07-02

申请号：US16255786

申请日：2019-01-23

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chung-Liang Chu ,  Chih-Hsien Tang ,  Yu-Ruei Chen ,  Ya-Huei Tsai ,  Rai-Min Huang ,  Chueh-Fei Tai

IPC: H01L27/02 ,  H01L27/22 ,  H01L43/02 ,  H01L43/12 ,  G03F1/36

Abstract: A layout pattern for magnetoresistive random access memory (MRAM) includes: a first magnetic tunneling junction (MTJ) pattern on a substrate; a second MTJ pattern adjacent to the first MTJ pattern; and a first metal interconnection pattern between the first MTJ pattern and the second MTJ pattern, wherein the first MTJ pattern, the first metal interconnection pattern, and the second MTJ pattern comprise a staggered arrangement.

公开(公告)号：US09583568B2

公开(公告)日：2017-02-28

申请号：US14612300

申请日：2015-02-03

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： En-Chiuan Liou ,  Ssu-I Fu ,  Chia-Lin Lu ,  Shih-Hung Tsai ,  Chih-Wei Yang ,  Chia-Ching Lin ,  Chia-Hsun Tseng ,  Rai-Min Huang

IPC: H01L29/66 ,  H01L21/84 ,  H01L27/06 ,  H01L29/78 ,  H01L29/06 ,  H01L21/762 ,  H01L27/12 ,  H01L21/76

CPC classification number: H01L29/0684 ,  H01L21/76 ,  H01L21/762 ,  H01L21/76232 ,  H01L27/1211 ,  H01L29/0649 ,  H01L29/6681 ,  H01L29/7846 ,  H01L29/7851

Abstract: The present invention provides a semiconductor structure, including a substrate, a shallow trench isolation (STI) disposed in the substrate, a plurality of first fin structures disposed in the substrate, where each first fin structure and the substrate have same material, and a plurality of second fin structures disposed in the STI, where each second fin structure and the STI have same material.

Abstract translation: 本发明提供一种半导体结构，包括基板，设置在基板中的浅沟槽隔离（STI），设置在基板中的多个第一翅片结构，其中每个第一翅片结构和基板具有相同的材料，以及多个 设置在STI中的第二鳍结构，其中每个第二鳍结构和STI具有相同的材料。

公开(公告)号：US20160276429A1

公开(公告)日：2016-09-22

申请号：US14684445

申请日：2015-04-13

Applicant: United Microelectronics Corp.

Inventor： I-Ming Tseng ,  Wen-An Liang ,  Rai-Min Huang ,  Chen-Ming Huang ,  Tong-Jyun Huang ,  Kuan-Hsien Li

IPC: H01L29/06 ,  H01L29/66 ,  H01L21/762 ,  H01L29/78 ,  H01L21/8234

CPC classification number: H01L29/66545 ,  H01L21/76224 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823481 ,  H01L27/0886 ,  H01L29/7851

Abstract: A semiconductor device and a method of forming the same, the semiconductor device includes a fin shaped structure, a spacer layer and a dummy gate structure. The fin shaped structure is disposed on a substrate, wherein the fin shaped structure has a trench. The spacer layer is disposed on sidewalls of the trench. The dummy gate structure is disposed across the trench and includes a portion thereof disposed in the trench.

Abstract translation: 半导体器件及其形成方法，半导体器件包括鳍状结构，间隔层和虚拟栅极结构。 鳍状结构设置在基板上，其中鳍状结构具有沟槽。 间隔层设置在沟槽的侧壁上。 伪栅极结构跨越沟槽设置并且包括其设置在沟槽中的部分。

公开(公告)号：US09093465B2

公开(公告)日：2015-07-28

申请号：US14102515

申请日：2013-12-11

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yu-Ting Li ,  Po-Cheng Huang ,  Wu-Sian Sie ,  Chun-Hsiung Wang ,  Yi-Liang Liu ,  Chia-Lin Hsu ,  Rai-Min Huang

IPC: H01L21/3205 ,  H01L29/66 ,  H01L21/321 ,  H01L21/02

CPC classification number: H01L29/66545 ,  H01L21/02074 ,  H01L21/02112 ,  H01L21/02318 ,  H01L21/32055 ,  H01L21/3212 ,  H01L29/66795

Abstract: A method of fabricating a semiconductor device includes the following steps. A substrate including at least a fin structure is provided, and a material layer is formed to cover the fin structure. Then, a first planarization process is performed on the material layer to form a first material layer, and an oxide layer is formed on the first material layer. Subsequently, the oxide layer is totally removed to expose the first material layer, and a second material layer is formed in-situ on the first material layer after totally removing the oxide layer.

Abstract translation: 制造半导体器件的方法包括以下步骤。 提供至少包括翅片结构的基板，并且形成材料层以覆盖翅片结构。 然后，在材料层上进行第一平面化处理以形成第一材料层，并且在第一材料层上形成氧化物层。 随后，完全除去氧化物层以露出第一材料层，并且在完全除去氧化物层之后，在第一材料层上原位形成第二材料层。

公开(公告)号：US20240373754A1

公开(公告)日：2024-11-07

申请号：US18203642

申请日：2023-05-30

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Jia-Rong Wu ,  I-Fan Chang ,  Rai-Min Huang ,  Po-Kai hsu

IPC: H10N50/01 ,  H10N50/80

Abstract: The invention provides a semiconductor structure, which comprises a plurality of magnetic tunnel junction (MTJ) elements. Seen from a top view, the MTJ elements are arranged in an array, at least one second contact structure is located in the array arranged by the MTJ elements, and at least one first mask layer covers a top surface and two sidewalls of each MTJ element, when seen from a cross-sectional view, a sidewall of the first mask layer is aligned with a sidewall of a second metal layer which is disposed below the second contact structure.

公开(公告)号：US20230337551A1

公开(公告)日：2023-10-19

申请号：US17743459

申请日：2022-05-13

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Jia-Rong Wu ,  Chi-Hsuan Cheng ,  Rai-Min Huang ,  Po-Kai Hsu

IPC: H01L43/14 ,  H01L27/22 ,  H01L43/04 ,  H01L43/06

CPC classification number: H01L43/14 ,  H01L27/222 ,  H01L43/04 ,  H01L43/06

Abstract: A method for fabricating semiconductor device includes the steps of first forming a magnetic tunneling junction (MTJ) on a substrate, forming a first spin orbit torque (SOT) layer on the MTJ, forming an inter-metal dielectric (IMD) layer around the first SOT layer, forming a second SOT layer on the IMD layer, forming a first hard mask on the second SOT layer, patterning the first hard mask along a first direction, and then patterning the first hard mask along a second direction.