公开(公告)号：US09412734B2

公开(公告)日：2016-08-09

申请号：US14588991

申请日：2015-01-05

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Zhibiao Zhou ,  Shao-Hui Wu ,  Chi-Fa Ku

IPC: H01L27/06 ,  H01L49/02

CPC classification number: H01L28/60 ,  H01L28/10 ,  H01L28/87 ,  H01L28/91

Abstract: A structure with an inductor and a MIM capacitor is provided. The structure includes a dielectric layer, an inductor and a MIM capacitor. The inductor and the MIM capacitor are disposed within the dielectric layer. The inductor includes a core and a wire surrounding the core. The MIM capacitor includes a top electrode, a bottom electrode and an insulating layer. The top electrode or the bottom electrode includes a material which forms the core.

Abstract translation: 提供具有电感器和MIM电容器的结构。 该结构包括电介质层，电感器和MIM电容器。 电感器和MIM电容器设置在电介质层内。 电感器包括芯和围绕芯的导线。 MIM电容器包括顶电极，底电极和绝缘层。 顶部电极或底部电极包括形成芯的材料。

公开(公告)号：US20160211187A1

公开(公告)日：2016-07-21

申请号：US14598236

申请日：2015-01-16

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Xing Hua Zhang ,  Chi-Fa Ku ,  Hong Liao ,  Ye Chao Li ,  Hui Yang

IPC: H01L21/66 ,  H01L23/10 ,  H01L23/528 ,  G06F17/50

CPC classification number: G06F17/5081 ,  H01L21/823871 ,  H01L22/34 ,  H01L23/10 ,  H01L23/528 ,  H01L23/562 ,  H01L23/58 ,  H01L27/0266 ,  H01L27/0629 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor monitoring device includes a substrate, a die seal ring formed on the substrate, a deep n-typed well formed in the substrate under the die seal ring, and a monitoring device electrically connected to the die seal ring. The monitoring device is formed in a scribe line region defined on the substrate. A width of the deep n-typed well is larger than a width of the die seal ring.

Abstract translation: 半导体监视装置包括基板，形成在基板上的模具密封环，形成在模具密封环下方的基板中的深n型阱，以及与模密封环电连接的监视装置。 监测装置形成在限定在基板上的划线区域中。 深n型井的宽度大于模具密封环的宽度。

公开(公告)号：US20150137323A1

公开(公告)日：2015-05-21

申请号：US14080798

申请日：2013-11-15

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： ZHIBIAO ZHOU ,  Shao-Hui Wu ,  Chi-Fa Ku

IPC: H01L21/768 ,  H01L23/48

CPC classification number: H01L21/76898 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method for fabricating through silicon via (TSV) structure is disclosed. The method includes the steps of: providing a substrate; forming a through-silicon via (TSV) in the substrate; depositing a liner in the TSV; removing the liner in a bottom of the TSV; and filling a first conductive layer in the TSV for forming a TSV structure.

Abstract translation: 公开了一种通过硅通孔（TSV）制造方法。 该方法包括以下步骤：提供衬底; 在衬底中形成穿硅通孔（TSV）; 在TSV中沉积衬垫; 移除TSV底部的衬垫; 以及在TSV中填充用于形成TSV结构的第一导电层。

公开(公告)号：US20190027607A1

公开(公告)日：2019-01-24

申请号：US16131014

申请日：2018-09-13

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： ZHIBIAO ZHOU ,  Shao-Hui Wu ,  Chi-Fa Ku

IPC: H01L29/786 ,  H01L29/66 ,  H01L29/51 ,  H01L29/49 ,  H01L27/12 ,  H01L29/24 ,  H01L29/06 ,  H01L29/04

Abstract: The present invention provides a method for forming a semiconductor structure, the method includes: firstly, a substrate having a recess disposed therein is provided, wherein the substrate comprises a silicon substrate, next, a first element is formed in the recess and arranged along a first direction, wherein the first element is made of an oxidation semiconductor material, afterwards, a dielectric layer is formed on the first element, and a second element is formed on dielectric layer and arranged along the first direction, wherein the second element is used as the gate structure of a transistor structure.

公开(公告)号：US10043917B2

公开(公告)日：2018-08-07

申请号：US15059311

申请日：2016-03-03

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Zhibiao Zhou ,  Shao-Hui Wu ,  Chen-Bin Lin ,  Ding-Lung Chen ,  Chi-Fa Ku

IPC: H01L21/00 ,  H01L29/786 ,  H01L29/66 ,  H01L21/426

Abstract: An oxide semiconductor device and a method for manufacturing the same are provided in the present invention. The oxide semiconductor device includes a back gate, an oxide semiconductor film, a pair of source and drain electrodes, agate insulating film, a gate electrode on the oxide semiconductor film with the gate insulating film therebetween, an insulating layer covering only over the gate electrode and the pair of source and drain electrodes, and a top blocking film over the insulating layer.

公开(公告)号：US09893066B2

公开(公告)日：2018-02-13

申请号：US15432165

申请日：2017-02-14

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Zhi-Biao Zhou ,  Shao-Hui Wu ,  Chi-Fa Ku ,  Chen-Bin Lin ,  Su Xing ,  Tien-Yu Hsieh

IPC: H01L29/49 ,  H01L27/105 ,  H01L27/12 ,  H01L29/786

CPC classification number: H01L27/1052 ,  H01L27/108 ,  H01L27/115 ,  H01L27/1225 ,  H01L27/124 ,  H01L27/1255 ,  H01L28/40 ,  H01L29/66742 ,  H01L29/7869

Abstract: A semiconductor transistor device includes an oxide semiconductor layer having an active surface, a source electrode, a drain electrode, a gate electrode and a control capacitor. The gate electrode, the source electrode and the drain electrode are directly in contact with the active surface. The gate electrode is disposed between the drain electrode and the source electrode. The gate electrode, the source electrode and the drain electrode are separated from each other. The control capacitor is electrically connected to the gate electrode through a connection.

公开(公告)号：US20170170257A1

公开(公告)日：2017-06-15

申请号：US15352551

申请日：2016-11-15

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： ZHIBIAO ZHOU ,  Shao-Hui Wu ,  Chi-Fa Ku ,  Chen-Bin Lin

IPC: H01L49/02

CPC classification number: H01L28/91 ,  H01L28/92

Abstract: A capacitor includes: a bottom electrode; a middle electrode on the bottom electrode; a top electrode on the middle electrode; a first dielectric layer between the bottom electrode and the middle electrode; and a second dielectric layer between the middle electrode and the top electrode. Preferably, the second dielectric layer is disposed on at least a sidewall of the middle electrode to physically contact the first dielectrically, and the middle electrode includes a H-shape.

公开(公告)号：US20170125599A1

公开(公告)日：2017-05-04

申请号：US14960041

申请日：2015-12-04

Applicant: United Microelectronics Corp.

Inventor： Hai-Biao Yao ,  Shao-Hui Wu ,  Chi-Fa Ku ,  Chen-Bin Lin ,  Zhi-Biao Zhou

IPC: H01L29/786 ,  H01L29/51 ,  H01L21/033 ,  H01L29/66 ,  H01L21/02

CPC classification number: H01L29/7869 ,  H01L21/02178 ,  H01L21/02181 ,  H01L21/02565 ,  H01L21/0332 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66795 ,  H01L29/66969 ,  H01L29/785 ,  H01L29/78606 ,  H01L29/78696

Abstract: A semiconductor device and a manufacturing method thereof are provided. The semiconductor device includes an oxide semiconductor protrusion, a source, a drain, an oxide semiconductor layer, a first O-barrier layer, a gate electrode, a second O-barrier layer, and an H-barrier layer. The oxide semiconductor protrusion is disposed on an oxide substrate. The source and the drain are respectively disposed on opposite ends of the oxide semiconductor protrusion. The oxide semiconductor layer is disposed on the oxide substrate and covers the oxide semiconductor protrusion, the source, and the drain. The first O-barrier layer is disposed on the oxide semiconductor layer. The gate electrode is disposed on the first O-barrier layer and across the oxide semiconductor protrusion. The second O-barrier layer is disposed on the gate electrode. The H-barrier layer is disposed on the oxide substrate and covers the second O-barrier layer.

公开(公告)号：US09627549B1

公开(公告)日：2017-04-18

申请号：US14874546

申请日：2015-10-05

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Zhi-Biao Zhou ,  Shao-Hui Wu ,  Chi-Fa Ku ,  Chen-Bin Lin ,  Su Xing ,  Tien-Yu Hsieh

IPC: H01L29/49 ,  H01L29/786 ,  H01L29/66 ,  H01L49/02 ,  H01L27/115 ,  H01L27/108

CPC classification number: H01L27/1052 ,  H01L27/108 ,  H01L27/115 ,  H01L27/1225 ,  H01L27/124 ,  H01L27/1255 ,  H01L28/40 ,  H01L29/66742 ,  H01L29/7869

Abstract: A semiconductor transistor device includes an oxide semiconductor layer having an active surface, a source electrode, a drain electrode, a gate electrode and a control capacitor. The gate electrode, the source electrode and the drain electrode are directly in contact with the active surface. The gate electrode is disposed between the drain electrode and the source electrode. The gate electrode, the source electrode and the drain electrode are separated from each other. The control capacitor is electrically connected to the gate electrode through a connection.

公开(公告)号：US09627547B2

公开(公告)日：2017-04-18

申请号：US14724799

申请日：2015-05-28

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Zhibiao Zhou ,  Shao-Hui Wu ,  Chi-Fa Ku

IPC: H01L29/10 ,  H01L29/786 ,  H01L29/24 ,  H01L29/04 ,  H01L29/49 ,  H01L29/51

CPC classification number: H01L29/7869 ,  H01L27/1218 ,  H01L27/1225 ,  H01L29/045 ,  H01L29/0649 ,  H01L29/24 ,  H01L29/4908 ,  H01L29/4916 ,  H01L29/517 ,  H01L29/66969 ,  H01L29/78603

Abstract: A semiconductor structure includes a substrate and a first element disposed in the substrate and arranged along a first direction. The first element is made of a semiconductor oxide material. The semiconductor structure also includes a dielectric layer disposed on the first element, and a second element, disposed on the dielectric layer and arranged along the first direction. The second element is used as a gate of a transistor structure.