公开(公告)号：US20210013325A1

公开(公告)日：2021-01-14

申请号：US16544830

申请日：2019-08-19

申请人： UNITED MICROELECTRONICS CORP.

发明人： Chuan-Chang Wu ,  Zhen Wu ,  Hsuan-Hsu Chen ,  Chun-Lung Chen

IPC分类号： H01L29/66 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L21/02 ,  H01L21/306 ,  H01L21/764

摘要： A manufacturing method of a semiconductor device includes the following steps. First patterned structures are formed on a substrate. Each of the first patterned structures includes a first semiconductor pattern and a first bottom protection pattern disposed between the first semiconductor pattern and the substrate. A first protection layer is formed on the first patterned structures and the substrate. A part of the first protection layer is located between the first patterned structures. A first opening is formed in the first protection layer between the first patterned structures. The first opening penetrates the first protection layer and exposes a part of the substrate. A first etching process is performed after forming the first opening. A part of the substrate under the first patterned structures is removed by the first etching process for suspending at least a part of each of the first patterned structures above the substrate.

公开(公告)号：US20200212290A1

公开(公告)日：2020-07-02

申请号：US16255754

申请日：2019-01-23

申请人： UNITED MICROELECTRONICS CORP.

发明人： Hui-Lin Wang ,  Tai-Cheng Hou ,  Wei-Xin Gao ,  Fu-Yu Tsai ,  Chin-Yang Hsieh ,  Chen-Yi Weng ,  Jing-Yin Jhang ,  Bin-Siang Tsai ,  Kun-Ju Li ,  Chih-Yueh Li ,  Chia-Lin Lu ,  Chun-Lung Chen ,  Kun-Yuan Liao ,  Yu-Tsung Lai ,  Wei-Hao Huang

IPC分类号： H01L41/47 ,  H01L21/762 ,  H01L43/02 ,  H01L21/768

摘要： A method for fabricating semiconductor device includes the steps of: forming a first magnetic tunneling junction (MTJ) on a substrate; forming a first ultra low-k (ULK) dielectric layer on the first MTJ; performing a first etching process to remove part of the first ULK dielectric layer and forming a damaged layer on the first ULK dielectric layer; and forming a second ULK dielectric layer on the damaged layer.

公开(公告)号：US10199374B2

公开(公告)日：2019-02-05

申请号：US15825057

申请日：2017-11-28

申请人： UNITED MICROELECTRONICS CORP.

发明人： Chia-Lin Lu ,  Chun-Lung Chen ,  Kun-Yuan Liao ,  Hsiang-Hung Peng ,  Wei-Hao Huang ,  Ching-Wen Hung ,  Chih-Sen Huang

IPC分类号： H01L27/06 ,  H01L21/768 ,  H01L21/8234 ,  H01L49/02

摘要： A method for fabricating semiconductor device is disclosed. A substrate having a first transistor on a first region, a second transistor on a second region, a trench isolation region, a resistor-forming region is provided. A first ILD layer covers the first region, the second region, and the resistor-forming region. A resistor material layer and a capping layer are formed over the first region, the second region, and the resistor-forming region. The capping layer and the resistor material layer are patterned to form a first hard mask pattern above the first and second regions and a second hard mask pattern above the resistor-forming region. The resistor material layer is isotropically etched. A second ILD layer is formed over the substrate. The second ILD layer and the first ILD layer are patterned with a mask and the first hard mask pattern to form a contact opening.

公开(公告)号：US09799550B2

公开(公告)日：2017-10-24

申请号：US14845294

申请日：2015-09-04

申请人： UNITED MICROELECTRONICS CORP.

发明人： Wei-Hao Huang ,  Chia-Lin Lu ,  Chun-Lung Chen ,  Kun-Yuan Liao ,  Feng-Yi Chang ,  Chieh-Te Chen ,  Shang-Yuan Tsai

IPC分类号： H01L21/02 ,  H01L21/441 ,  H01L21/768 ,  H01L21/311 ,  H01L21/033 ,  H01L29/417 ,  H01L29/78

CPC分类号： H01L21/76802 ,  H01L21/0332 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/31138 ,  H01L21/31144 ,  H01L21/32134 ,  H01L21/76877 ,  H01L21/76897 ,  H01L29/41791 ,  H01L2029/7858

摘要： The present invention provides a method for forming an opening, including: first, a hard mask material layer is formed on a target layer, next, a tri-layer hard mask is formed on the hard mask material layer, where the tri-layer hard mask includes an bottom organic layer (ODL), a middle silicon-containing hard mask bottom anti-reflection coating (SHB) layer and a top photoresist layer, and an etching process is then performed, to remove parts of the tri-layer hard mask, parts of the hard mask material layer and parts of the target layer in sequence, so as to form at least one opening in the target layer, where during the step for removing parts of the hard mask material layer, a lateral etching rate of the hard mask material layer is smaller than a lateral etching rate of the ODL.

公开(公告)号：US09728455B2

公开(公告)日：2017-08-08

申请号：US15404163

申请日：2017-01-11

申请人： UNITED MICROELECTRONICS CORP.

发明人： Chia-Lin Lu ,  Chun-Lung Chen ,  Kun-Yuan Liao ,  Feng-Yi Chang ,  Chieh-Te Chen

IPC分类号： H01L21/20 ,  H01L21/768 ,  H01L23/535 ,  H01L23/532

CPC分类号： H01L21/76895 ,  H01L21/76805 ,  H01L21/76885 ,  H01L21/76897 ,  H01L23/485 ,  H01L23/53295 ,  H01L23/535 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for fabricating semiconductor device includes the steps of: providing a substrate having a gate structure thereon and an interlayer dielectric (ILD) layer surrounding the gate structure; forming a sacrificial layer on the gate structure; forming a first contact plug in the sacrificial layer and the ILD layer; removing the sacrificial layer; and forming a first dielectric layer on the gate structure and the first contact plug.

公开(公告)号：US09543203B1

公开(公告)日：2017-01-10

申请号：US14791242

申请日：2015-07-02

申请人： UNITED MICROELECTRONICS CORP.

发明人： Chia-Lin Lu ,  Chun-Lung Chen ,  Kun-Yuan Liao ,  Feng-Yi Chang ,  En-Chiuan Liou ,  Chia-Hsun Tseng ,  Wei-Hao Huang ,  Yu-Ting Hung

IPC分类号： H01L21/3205 ,  H01L29/66 ,  H01L21/768 ,  H01L21/311 ,  H01L21/027

CPC分类号： H01L21/76897 ,  H01L21/0276 ,  H01L21/31133 ,  H01L21/31144 ,  H01L21/76802 ,  H01L21/76843 ,  H01L21/76877 ,  H01L29/66545 ,  H01L29/6656

摘要： A method of fabricating a semiconductor structure includes the following steps: forming a first interlayer dielectric on a substrate; forming a gate electrode on the substrate so that the periphery of the gate electrode is surrounded by the first interlayer dielectric; forming a patterned mask layer comprising at least a layer of organic material on the gate electrode; forming a conformal dielectric layer to conformally cover the layer of organic material; and forming a second interlayer dielectric to cover the conformal dielectric layer.

摘要翻译： 制造半导体结构的方法包括以下步骤：在衬底上形成第一层间电介质; 在所述基板上形成栅电极，使得所述栅电极的周围被所述第一层间电介质包围; 在所述栅电极上形成至少包含一层有机材料的图案化掩模层; 形成保形绝缘层以保形地覆盖有机材料层; 以及形成覆盖所述共形介电层的第二层间电介质。

公开(公告)号：US20170004997A1

公开(公告)日：2017-01-05

申请号：US14791242

申请日：2015-07-02

申请人： United Microelectronics Corp.

发明人： Chia-Lin Lu ,  Chun-Lung Chen ,  Kun-Yuan Liao ,  Feng-Yi Chang ,  En-Chiuan Liou ,  Chia-Hsun Tseng ,  Wei-Hao Huang ,  Yu-Ting Hung

IPC分类号： H01L21/768 ,  H01L21/311 ,  H01L21/027 ,  H01L29/66

CPC分类号： H01L21/76897 ,  H01L21/0276 ,  H01L21/31133 ,  H01L21/31144 ,  H01L21/76802 ,  H01L21/76843 ,  H01L21/76877 ,  H01L29/66545 ,  H01L29/6656

摘要： A method of fabricating a semiconductor structure includes the following steps: forming a first interlayer dielectric on a substrate; forming a gate electrode on the substrate so that the periphery of the gate electrode is surrounded by the first interlayer dielectric; forming a patterned mask layer comprising at least a layer of organic material on the gate electrode; forming a conformal dielectric layer to conformally cover the layer of organic material; and forming a second interlayer dielectric to cover the conformal dielectric layer.

摘要翻译： 制造半导体结构的方法包括以下步骤：在衬底上形成第一层间电介质; 在所述基板上形成栅电极，使得所述栅电极的周围被所述第一层间电介质包围; 在所述栅电极上形成至少包含一层有机材料的图案化掩模层; 形成保形绝缘层以保形地覆盖有机材料层; 以及形成覆盖所述共形介电层的第二层间电介质。

公开(公告)号：US09530851B1

公开(公告)日：2016-12-27

申请号：US14841661

申请日：2015-08-31

申请人： UNITED MICROELECTRONICS CORP.

发明人： Chia-Lin Lu ,  Chun-Lung Chen ,  En-Chiuan Liou ,  Chih-Wei Yang ,  Yu-Cheng Tung ,  Kun-Yuan Liao ,  Feng-Yi Chang

IPC分类号： H01L29/78 ,  H01L21/8238 ,  H01L29/423 ,  H01L27/088 ,  H01L21/8234

CPC分类号： H01L29/42364 ,  H01L21/823468 ,  H01L21/823475 ,  H01L27/088 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/7843

摘要： The present invention provides a semiconductor device, including at least two gate structures, and each gate structure includes a gate, a spacer and a source/drain region, the source/drain region disposed on two sides of the gate. A first dielectric layer is disposed on the substrate and between two gate structures, where the first dielectric layer has a concave surface, and the first dielectric layer directly contacts the spacer. A floating spacer is disposed on the first dielectric layer and on a sidewall of the gate, and at least one contact plug is disposed on the source/drain region, where the contact plug directly contacts the floating spacer.

摘要翻译： 本发明提供一种包括至少两个栅极结构的半导体器件，并且每个栅极结构包括栅极，间隔物和源极/漏极区域，源极/漏极区域设置在栅极的两侧。 第一电介质层设置在衬底上并且在两个栅极结构之间，其中第一电介质层具有凹面，并且第一电介质层直接接触间隔物。 浮动间隔物设置在第一介电层上和栅极的侧壁上，并且至少一个接触插塞设置在源极/漏极区上，其中接触插塞直接接触浮动间隔物。

公开(公告)号：US20160064528A1

公开(公告)日：2016-03-03

申请号：US14509070

申请日：2014-10-08

申请人： UNITED MICROELECTRONICS CORP.

发明人： Chia-Lin Lu ,  Chun-Lung Chen ,  Kun-Yuan Liao ,  Feng-Yi Chang

IPC分类号： H01L29/66 ,  H01L29/78

CPC分类号： H01L29/66795 ,  H01L29/66545 ,  H01L29/785

摘要： A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having a metal gate thereon and a hard mask atop the metal gate; and performing a high-density plasma (HDP) process to form a cap layer on the hard mask and the substrate.

摘要翻译： 公开了半导体器件的制造方法。 该方法包括以下步骤：提供其上具有金属栅极的基板和在金属栅极顶部的硬掩模; 以及执行高密度等离子体（HDP）工艺以在硬掩模和基板上形成盖层。

公开(公告)号：US09263294B2

公开(公告)日：2016-02-16

申请号：US14273283

申请日：2014-05-08

申请人： United Microelectronics Corp.

发明人： Chia-Lin Lu ,  Chun-Lung Chen ,  Kun-Yuan Liao ,  Feng-Yi Chang ,  Chieh-Te Chen ,  Cheng-Hsing Chuang

IPC分类号： H01L21/4763 ,  H01L21/311

CPC分类号： H01L21/31111 ,  H01L21/31133 ,  H01L21/31144 ,  H01L21/76816 ,  H01L21/76897

摘要： A method of forming a semiconductor device is provided. A material layer, a first flowing material layer and a first mask layer are sequentially formed on a substrate. A first etching process is performed by using the first mask layer as a mask, so as to form a first opening in the material layer. The first mask layer and the first flowing material layer are removed. A filler layer is formed in the first opening. A second flowing material layer is formed on the material layer and the filler layer. A second mask layer is formed on the second flowing material layer. A second etching process is performed by using the second mask layer as a mask, so as to form a second opening in the material layer.

摘要翻译： 提供一种形成半导体器件的方法。 在基板上依次形成材料层，第一流动材料层和第一掩模层。 通过使用第一掩模层作为掩模来进行第一蚀刻工艺，以在材料层中形成第一开口。 去除第一掩模层和第一流动材料层。 在第一开口中形成填充层。 在材料层和填料层上形成第二流动材料层。 在第二流动材料层上形成第二掩模层。 通过使用第二掩模层作为掩模来进行第二蚀刻处理，以在材料层中形成第二开口。