公开(公告)号：US09882054B2

公开(公告)日：2018-01-30

申请号：US14981869

申请日：2015-12-28

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： En-Chiuan Liou ,  Yu-Cheng Tung

IPC: H01L29/78 ,  H01L29/08 ,  H01L29/06 ,  H01L29/16 ,  H01L29/161 ,  H01L29/165 ,  H01L21/306 ,  H01L29/66 ,  H01L21/768 ,  H01L21/02

CPC classification number: H01L29/785 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/30604 ,  H01L21/76897 ,  H01L21/823431 ,  H01L21/823481 ,  H01L29/0649 ,  H01L29/0657 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66636 ,  H01L29/66795

Abstract: A FinFET is provided. The FinFET includes a substrate. A plurality of fin structures are defined on the substrate. A gate structure crosses each fin structure. Two first recesses are disposed on two sides of the gate structure respectively, wherein each first recess further includes a plurality of second recesses disposed therein, and the position of each second recess corresponds to each fin structure. Two epitaxial layers are disposed at two sides of the gate structure respectively and in the first recesses, each epitaxial layer has a bottom surface including a second concave and convex profile, and each epitaxial layer directly contacts a bottom surface of each first recess and a bottom surface of each second recess.

公开(公告)号：US09870994B2

公开(公告)日：2018-01-16

申请号：US14489461

申请日：2014-09-17

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yu-Cheng Tung

IPC: H01L23/532 ,  H01L21/768 ,  H01L21/311

CPC classification number: H01L23/53238 ,  H01L21/31144 ,  H01L21/76834 ,  H01L21/76849 ,  H01L21/76885 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate; forming an ultra low-k (ULK) dielectric layer on the substrate; forming a hard mask on the ULK dielectric layer; forming an opening in the hard mask and the ULK dielectric layer; forming a conductive layer in the opening and on the hard mask; planarizing the conductive layer; and removing the hard mask to expose the ULK dielectric layer so that the top surface of the ULK dielectric layer is lower than the top surface of the conductive layer.

公开(公告)号：US20170278928A1

公开(公告)日：2017-09-28

申请号：US15152570

申请日：2016-05-12

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yu-Cheng Tung

IPC: H01L29/10 ,  H01L29/06 ,  H01L21/762 ,  H01L29/66 ,  H01L21/02 ,  H01L21/308 ,  H01L29/78 ,  H01L29/165

CPC classification number: H01L29/1054 ,  H01L21/02634 ,  H01L21/3085 ,  H01L21/76278 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/165 ,  H01L29/66795 ,  H01L29/6681 ,  H01L29/785

Abstract: The present invention provides a semiconductor device, including a substrate, a first semiconductor layer, a plurality of first sub recess, a plurality of insulation structures and a first top semiconductor layer. The substrate has a first region disposed within an STI. The first semiconductor layer is disposed in the first region. The first sub recesses are disposed in the first semiconductor layer. The insulation structures are disposed on the first semiconductor layer. The first top semiconductor layer forms a plurality of fin structures, which are embedded in the first sub recesses, arranged alternatively with the insulation structures and protruding over the insulation structures.

公开(公告)号：US20170278845A1

公开(公告)日：2017-09-28

申请号：US15134367

申请日：2016-04-20

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yu-Cheng Tung

IPC: H01L27/092 ,  H01L21/762 ,  H01L21/306 ,  H01L29/165 ,  H01L29/267 ,  H01L21/8238 ,  H01L29/06

CPC classification number: H01L27/0924 ,  H01L21/30625 ,  H01L21/76224 ,  H01L21/823821 ,  H01L21/823878 ,  H01L29/0649 ,  H01L29/165 ,  H01L29/267

Abstract: A method for fabricating semiconductor device is disclosed. First, a substrate is provided, a first fin-shaped structure and a bump are formed on the substrate, and an insulating layer is formed on the bump and around the first fin-shaped structure. Next, a part of the first fin-shaped structure is removed, an epitaxial layer is formed on the first fin-shaped structure, part of the epitaxial layer is removed, and part of the insulating layer is removed to form a shallow trench isolation (STI) and a second fin-shaped structure protruding from the STI. Preferably, the second fin-shaped structure includes a top portion and a bottom portion, in which the bottom portion and the bump are made of same material.

公开(公告)号：US09772557B2

公开(公告)日：2017-09-26

申请号：US14714357

申请日：2015-05-18

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： En-Chiuan Liou ,  Yu-Cheng Tung

IPC: G03F7/20

CPC classification number: G03F7/203 ,  G03F7/2002 ,  G03F7/70091 ,  G03F7/70125 ,  G03F7/7025

Abstract: An illumination system includes a light source used to generate a light and an opaque plate. The opaque plate is disposed between the light source and a photomask and includes an annular aperture and an aperture dipole. The annular aperture has an inner side and an outer side. The aperture dipole includes at least one first aperture and at least one second aperture. The first aperture and the second aperture connected to the annular aperture respectively and protruding out from the outer side of the annular aperture are disposed symmetrically with respect to a center of the annular aperture.

公开(公告)号：US20170194422A1

公开(公告)日：2017-07-06

申请号：US15011683

申请日：2016-02-01

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yu-Cheng Tung

IPC: H01L29/06 ,  H01L21/762 ,  H01L27/088 ,  H01L21/306 ,  H01L21/02 ,  H01L21/8234 ,  H01L21/311

CPC classification number: H01L29/0649 ,  H01L21/02532 ,  H01L21/30604 ,  H01L21/31111 ,  H01L21/76224 ,  H01L21/823431 ,  H01L21/823481 ,  H01L27/0886 ,  H01L29/66795 ,  H01L29/66818 ,  H01L29/785

Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having a plurality of fin-shaped structures thereon; forming a first shallow trench isolation (STI) between the fin-shaped structures and a second STI around the fin-shaped structures; removing part of the fin-shaped structures; and removing part of the first STI so that the top surfaces of the fin-shaped structures are higher than the top surface of the first STI and lower than the top surface of the second STI.

公开(公告)号：US09679816B2

公开(公告)日：2017-06-13

申请号：US15190209

申请日：2016-06-23

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： En-Chiuan Liou ,  Yu-Cheng Tung

IPC: H01L21/82 ,  H01L21/8234 ,  H01L21/308 ,  H01L27/088 ,  H01L29/06 ,  H01L29/78 ,  H01L29/66

CPC classification number: H01L21/823431 ,  H01L21/3081 ,  H01L21/3085 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/0688 ,  H01L29/66795 ,  H01L29/785

Abstract: A semiconductor device and a method of forming the same, the semiconductor device includes a substrate, a plurality of fin shaped structures and an insulating layer. The substrate has a fin field-effect transistor (finFET) region, a first region, a second region and a third region. The first region, the second region and the third region have a first surface, a second surface, and a third surface, respectively, where the first surface is relatively higher than the second surface and the second surface is relatively higher than the third surface. The fin shaped structures are disposed on a surface of the fin field-effect transistor region. The insulating layer covers the first surface, the second surface and the third surface.

公开(公告)号：US09627538B2

公开(公告)日：2017-04-18

申请号：US14509449

申请日：2014-10-08

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yen-Liang Wu ,  Yu-Cheng Tung ,  Jhen-Cyuan Li ,  Shui-Yen Lu

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/66 ,  H01L21/762

CPC classification number: H01L29/7851 ,  H01L21/76224 ,  H01L21/76229 ,  H01L29/0649 ,  H01L29/66795 ,  H01L29/7848

Abstract: A fin field effect transistor (FinFET) with improved electrical performance and a method of manufacturing the same are disclosed. A FinFET includes a substrate having a top surface and an insulation. At least a recessed fin is extended upwardly from the top surface of the substrate, and at least a gate stack is formed above the substrate, wherein the gate stack is extended perpendicularly to an extending direction of the recessed fin, and the recessed fin is outside the gate stack. The insulation includes a lateral portion adjacent to the recessed fin, and a central portion contiguous to the lateral portion, wherein a top surface of the lateral portion is higher than a top surface of the central portion. A top surface of the recessed fin is lower than the top surface of the central portion of the insulation.

公开(公告)号：US09576859B2

公开(公告)日：2017-02-21

申请号：US15255316

申请日：2016-09-02

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yu-Cheng Tung

IPC: H01L21/76 ,  H01L29/78 ,  H01L21/762 ,  H01L21/28 ,  H01L27/088 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/66 ,  H01L29/423 ,  H01L27/092

CPC classification number: H01L21/823821 ,  H01L21/823431 ,  H01L21/823456 ,  H01L21/823481 ,  H01L21/823814 ,  H01L21/823842 ,  H01L21/823878 ,  H01L27/0886 ,  H01L27/092 ,  H01L27/0924 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/42364 ,  H01L29/4916 ,  H01L29/495 ,  H01L29/66545 ,  H01L29/66795

Abstract: A method for fabricating a semiconductor device comprises: Firstly, a semiconductor fin comprising a first sub-fin and a second sub-fin protruding from a surface of a substrate is provided. An isolation structure having an opening extending therein is then provided in the semiconductor fin to electrically isolate the first sub-fin and the second sub-fin. Subsequently, a first dummy structure disposed on the first isolation structure and having at least one metal layer entirely overlapping on the first isolation structure along a long axis of the semiconductor fin is formed, wherein the metal layer laterally conformally extends downwards into the opening and extends upwards beyond the first isolation structure along the long axis of the semiconductor fin, so as to form a stepped structure overlapping on sidewalls and a bottom of the opening, a portion of the first sub-fin and a portion of the second sub-fin.

Abstract translation: 一种制造半导体器件的方法包括：首先，提供包括从衬底表面突出的第一子鳍和第二副鳍的半导体鳍。 然后在半导体翅片中设置具有延伸在其中的开口的隔离结构，以电隔离第一子鳍和第二子鳍。 随后，形成第一虚拟结构，该第一虚拟结构设置在第一隔离结构上并具有沿着半导体鳍片的长轴与第一隔离结构完全重叠的至少一个金属层，其中金属层侧向共形地向下延伸到开口中并延伸 沿着半导体鳍片的长轴向上超过第一隔离结构，以形成在开口的侧壁和底部上重叠的阶梯结构，第一子鳍片的一部分和第二子鳍片的一部分。

公开(公告)号：US09490341B2

公开(公告)日：2016-11-08

申请号：US14704994

申请日：2015-05-06

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： En-Chiuan Liou ,  Chih-Wei Yang ,  Yu-Cheng Tung

IPC: H01L29/66 ,  H01L21/28 ,  H01L29/423

CPC classification number: H01L29/42376 ,  H01L21/28008 ,  H01L21/28088 ,  H01L21/76834 ,  H01L21/76897 ,  H01L29/4232 ,  H01L29/4966 ,  H01L29/6653 ,  H01L29/66545

Abstract: A method for manufacturing a semiconductor device having metal gate includes following steps. A substrate is provided. At least a transistor including a dummy gate is formed on the substrate and the transistor is embedded in an interlayer dielectric (ILD) layer. A first removal process is performed to remove a portion of the dummy gate to form a first recess in the transistor. An etching process is subsequently performed to remove a portion of the ILD layer to widen the first recess and to form a widened first recess. A second removal process is subsequently performed to remove the dummy gate entirely and to form a second recess in the transistor. A metal gate is formed in the second recess and followed by forming an insulating cap layer on the metal gate.

Abstract translation: 一种制造具有金属栅极的半导体器件的方法包括以下步骤。 提供基板。 在衬底上形成至少包括伪栅极的晶体管，并且将晶体管嵌入在层间电介质层（ILD）层中。 执行第一去除处理以去除伪栅极的一部分以在晶体管中形成第一凹部。 随后进行蚀刻处理以去除ILD层的一部分以加宽第一凹部并形成加宽的第一凹部。 随后执行第二去除处理以完全去除伪栅极并在晶体管中形成第二凹槽。 在第二凹部中形成金属栅极，然后在金属栅极上形成绝缘盖层。