公开(公告)号：US20200212290A1

公开(公告)日：2020-07-02

申请号：US16255754

申请日：2019-01-23

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hui-Lin Wang ,  Tai-Cheng Hou ,  Wei-Xin Gao ,  Fu-Yu Tsai ,  Chin-Yang Hsieh ,  Chen-Yi Weng ,  Jing-Yin Jhang ,  Bin-Siang Tsai ,  Kun-Ju Li ,  Chih-Yueh Li ,  Chia-Lin Lu ,  Chun-Lung Chen ,  Kun-Yuan Liao ,  Yu-Tsung Lai ,  Wei-Hao Huang

IPC: H01L41/47 ,  H01L21/762 ,  H01L43/02 ,  H01L21/768

Abstract: A method for fabricating semiconductor device includes the steps of: forming a first magnetic tunneling junction (MTJ) on a substrate; forming a first ultra low-k (ULK) dielectric layer on the first MTJ; performing a first etching process to remove part of the first ULK dielectric layer and forming a damaged layer on the first ULK dielectric layer; and forming a second ULK dielectric layer on the damaged layer.

公开(公告)号：US10276443B2

公开(公告)日：2019-04-30

申请号：US15445928

申请日：2017-02-28

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shin-Chi Chen ,  Chih-Chung Chen ,  An-Chi Liu ,  Chih-Yueh Li ,  Pei-Ching Yeh ,  Tsung-Chieh Yang

IPC: H01L21/8234 ,  H01L27/088 ,  H01L29/06 ,  H01L21/311 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/306 ,  H01L21/762 ,  H01L29/66 ,  H01L29/78

Abstract: A method of removing a fin structure includes providing a substrate. A fin structure extends from the substrate. A mask layer is disposed on a top surface of the fin structure. An organic dielectric layer covers the substrate, the fin structure and the mask layer. A first etching process is performed to entirely remove the mask layer by taking the organic dielectric layer as a mask. Then a second etching process is performed to remove the fin structure. The first etching process is preferably an anisotropic etching process, and the second etching process is an isotropic etching process.

公开(公告)号：US09613796B2

公开(公告)日：2017-04-04

申请号：US14818293

申请日：2015-08-04

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Tai-Heng Yu ,  Chih-Yueh Li

IPC: H01L21/306 ,  H01L21/02 ,  H01L21/308 ,  H01L21/67 ,  H01L21/687

CPC classification number: H01L21/02021 ,  H01L21/02087 ,  H01L21/30625 ,  H01L21/3083 ,  H01L21/6708 ,  H01L21/68735

Abstract: The wafer bevel etching apparatus of the present invention includes a wafer-protecting mask to cover parts of a wafer. A central region and a wafer bevel region surrounding the central region are defined on the wafer. The wafer-protecting mask includes a center sheltering region and at least one wafer bevel sheltering region. The center sheltering region can completely shelter the central region of the wafer, and the wafer bevel sheltering region extends from the outside edge of the center sheltering region, shelters parts of the wafer bevel region, and exposes the other parts of the wafer bevel region.

公开(公告)号：US09548268B2

公开(公告)日：2017-01-17

申请号：US14731394

申请日：2015-06-04

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chun-Chi Huang ,  Yung-Hung Yen ,  Hsin-Hsing Chen ,  Chih-Yueh Li ,  Tsun-Min Cheng

IPC: H01L23/522 ,  H01L23/528 ,  H01L23/532

CPC classification number: H01L23/5226 ,  H01L23/528 ,  H01L23/53238 ,  H01L23/53295

Abstract: A semiconductor device includes an opening, a metal nitride layer, a bilayer metal layer and a conductive bulk layer. The opening is disposed in a first dielectric layer. The metal nitride layer is disposed in the opening. The bilayer metal layer is disposed on the metal nitride layer in the opening, where the bilayer metal layer includes a first metal layer and a second metal layer which is disposed on the first metal layer and has a greater metal concentration than that of the first metal layer. The conductive bulk layer is filled in the opening.

Abstract translation: 半导体器件包括开口，金属氮化物层，双层金属层和导电体层。 开口设置在第一电介质层中。 金属氮化物层设置在开口中。 双层金属层设置在开口中的金属氮化物层上，其中双层金属层包括第一金属层和设置在第一金属层上并且具有比第一金属的金属浓度更大的金属浓度的第二金属层 层。 导电体层填充在开口中。

公开(公告)号：US09305847B2

公开(公告)日：2016-04-05

申请号：US14314425

申请日：2014-06-25

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shin-Chi Chen ,  Chih-Yueh Li ,  Shui-Yen Lu ,  Chi-Mao Hsu ,  Yuan-Chi Pai ,  Yu-Hong Kuo ,  Nien-Ting Ho

IPC: H01L21/8238 ,  H01L21/28 ,  H01L21/311 ,  H01L29/423

CPC classification number: H01L21/82385 ,  H01L21/28026 ,  H01L21/28088 ,  H01L21/31111 ,  H01L21/31144 ,  H01L21/32139 ,  H01L21/823842 ,  H01L29/42376 ,  H01L29/66545

Abstract: A method of manufacturing a semiconductor device is provided. The method includes the following steps. A substrate including a first transistor having a first conductivity type, a second transistor having a second conductivity type and a third transistor having the first conductivity type is formed. An inner-layer dielectric layer is formed on the substrate, and includes a first gate trench corresponding to the first transistor, a second gate trench corresponding to the second transistor and a third gate trench corresponding to the third transistor. A work function metal layer is formed on the inner-layer dielectric layer. An anti-reflective layer is coated on the work function metal layer. The anti-reflective layer on the second transistor and on the top portion of the third gate trench is removed to expose the work function metal layer. The exposed work function metal layer is removed.

Abstract translation: 提供一种制造半导体器件的方法。 该方法包括以下步骤。 形成包括具有第一导电类型的第一晶体管，具有第二导电类型的第二晶体管和具有第一导电类型的第三晶体管的衬底。 内层电介质层形成在衬底上，并且包括对应于第一晶体管的第一栅极沟槽，对应于第二晶体管的第二栅极沟槽和对应于第三晶体管的第三栅极沟槽。 在内层电介质层上形成功函数金属层。 在功函数金属层上涂布抗反射层。 去除第二晶体管上的抗反射层和第三栅极沟槽的顶部以暴露功函数金属层。 暴露的功能金属层被去除。

公开(公告)号：US20150064861A1

公开(公告)日：2015-03-05

申请号：US14016393

申请日：2013-09-03

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shin-Chi Chen ,  Chih-Yueh Li ,  Shui-Yen Lu ,  Yuan-Chi Pai ,  Fong-Lung Chuang

IPC: H01L29/66

CPC classification number: H01L29/66484 ,  H01L21/823412 ,  H01L21/823418 ,  H01L29/66477 ,  H01L29/66545 ,  H01L29/66628 ,  H01L29/66636

Abstract: A method for manufacturing a semiconductor device is provided. A substrate having a first gate and a second gate respectively formed in a first region and a second region is provided. An underlayer is formed on the substrate to cover the first gate in the first region and the second gate in the second region. A patterned mask with a predetermined thickness is formed on the underlayer in the first region. The underlayer corresponding to the second gate in the second region is removed by the patterned mask to expose the second gate, wherein the underlayer corresponding to the first gate in the first region is partially consumed to expose part of the first gate.

Abstract translation: 提供一种制造半导体器件的方法。 提供了分别形成在第一区域和第二区域中的具有第一栅极和第二栅极的衬底。 在衬底上形成底层以覆盖第一区域中的第一栅极和第二区域中的第二栅极。 在第一区域中的底层上形成具有预定厚度的图案化掩模。 通过图案化掩模去除对应于第二区域中的第二栅极的底层以暴露第二栅极，其中对应于第一区域中的第一栅极的底层被部分消耗以暴露第一栅极的部分。

公开(公告)号：US08883033B2

公开(公告)日：2014-11-11

申请号：US13784846

申请日：2013-03-05

Applicant: United Microelectronics Corp.

Inventor： Chi-Sheng Chen ,  Shin-Chi Chen ,  Chih-Yueh Li ,  Ted Ming-Lang Guo ,  Bo-Syuan Lee ,  Tsung-Hsun Tsai ,  Yu-Chin Cheng

IPC: B44C1/22 ,  H01L21/302 ,  H01L21/308

CPC classification number: H01L21/308 ,  H01L21/31111 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/6659

Abstract: A method for removing silicon nitride material includes following steps. A substrate having at least a gate structure formed thereon is provided, and at least a silicon nitride hard mask is formed on top of the gate structure. A first removal is performed to remove a portion of the silicon nitride hard mask with a first phosphoric acid (H3PO4) solution. A second removal is subsequently performed to remove remnant silicon nitride hard mask with a second phosphoric acid solution. The first removal and the second removal are performed in-situ. A temperature of the second phosphoric acid solution is lower than a temperature of the first phosphoric acid solution.

Abstract translation: 一种除去氮化硅材料的方法包括以下步骤。 提供了至少形成有栅极结构的衬底，并且在栅极结构的顶部上形成至少一个氮化硅硬掩模。 执行第一次去除以用第一磷酸（H 3 PO 4）溶液去除一部分氮化硅硬掩模。 随后进行第二次去除以用第二种磷酸溶液去除残留的氮化硅硬掩模。 第一次去除和第二次去除是原位进行的。 第二磷酸溶液的温度低于第一磷酸溶液的温度。