公开(公告)号：US20210296572A1

公开(公告)日：2021-09-23

申请号：US17341417

申请日：2021-06-08

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hui-Lin Wang ,  Chen-Yi Weng ,  Yi-Wei Tseng ,  Chin-Yang Hsieh ,  Jing-Yin Jhang ,  Yi-Hui Lee ,  Ying-Cheng Liu ,  Yi-An Shih ,  I-Ming Tseng ,  Yu-Ping Wang

IPC: H01L43/02 ,  H01L43/12

Abstract: A semiconductor device includes a magnetic tunneling junction (MTJ) on a substrate, a first spacer on one side of the of the MTJ, a second spacer on another side of the MTJ, a first metal interconnection on the MTJ, and a liner adjacent to the first spacer, the second spacer, and the first metal interconnection. Preferably, each of a top surface of the MTJ and a bottom surface of the first metal interconnection includes a planar surface and two sidewalls of the first metal interconnection are aligned with two sidewalls of the MTJ.

公开(公告)号：US20210202832A1

公开(公告)日：2021-07-01

申请号：US17204937

申请日：2021-03-18

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chen-Yi Weng ,  Jing-Yin Jhang ,  Hui-Lin Wang ,  Chin-Yang Hsieh

IPC: H01L43/12 ,  H01L43/10 ,  H01L27/22 ,  H01L43/02 ,  H01L43/08

Abstract: A manufacturing method of a semiconductor device includes the following steps. A first inter-metal dielectric (IMD) layer is formed on a substrate. A cap layer is formed on the first IMD layer. A connection structure is formed on the substrate and penetrates the cap layer and the first IMD layer. A magnetic tunnel junction (MTJ) stack is formed on the connection structure and the cap layer. A patterning process is performed to the MTJ stack for forming a MTJ structure on the connection structure and removing the cap layer. A spacer is formed on a sidewall of the MTJ structure and a sidewall of the connection structure. A second IMD layer is formed on the first IMD layer and surrounds the MTJ structure. The dielectric constant of the first IMD layer is lower than the dielectric constant of the second IMD layer.

公开(公告)号：US20210202828A1

公开(公告)日：2021-07-01

申请号：US17204961

申请日：2021-03-18

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chen-Yi Weng ,  Jing-Yin Jhang

IPC: H01L43/02 ,  H01L43/12 ,  H01F10/32 ,  H01F41/34 ,  H01L23/528 ,  H01L21/768 ,  H01L27/22 ,  H01L23/522

Abstract: A method for fabricating semiconductor device includes the steps of: forming a magnetic tunneling junction (MTJ) on a substrate; forming a liner on the MTJ; removing part of the liner to form a recess exposing the MTJ; and forming a conductive layer in the recess, wherein top surfaces of the conductive layer and the liner are coplanar. Preferably the MTJ further includes: a bottom electrode on the substrate, a fixed layer on the bottom electrode, and a top electrode on the fixed layer, in which the conductive layer and the top electrode are made of same material.

公开(公告)号：US20210119115A1

公开(公告)日：2021-04-22

申请号：US17134460

申请日：2020-12-27

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hui-Lin Wang ,  Tai-Cheng Hou ,  Wei-Xin Gao ,  Fu-Yu Tsai ,  Chin-Yang Hsieh ,  Chen-Yi Weng ,  Jing-Yin Jhang ,  Bin-Siang Tsai ,  Kun-Ju Li ,  Chih-Yueh Li ,  Chia-Lin Lu ,  Chun-Lung Chen ,  Kun-Yuan Liao ,  Yu-Tsung Lai ,  Wei-Hao Huang

IPC: H01L43/08 ,  H01L21/768 ,  H01L43/02 ,  H01L21/762

Abstract: A method for fabricating semiconductor device includes the steps of: forming a first magnetic tunneling junction (MTJ) on a substrate; forming a first ultra low-k (ULK) dielectric layer on the first MTJ; performing a first etching process to remove part of the first ULK dielectric layer and forming a damaged layer on the first ULK dielectric layer; and forming a second ULK dielectric layer on the damaged layer.

公开(公告)号：US20210074907A1

公开(公告)日：2021-03-11

申请号：US16589157

申请日：2019-10-01

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hui-Lin Wang ,  Po-Kai Hsu ,  Chen-Yi Weng ,  Jing-Yin Jhang ,  Yu-Ping Wang ,  Hung-Yueh Chen

IPC: H01L43/02 ,  H01L27/22 ,  H01L43/08 ,  H01L43/12

Abstract: A method for fabricating semiconductor device includes the steps of: forming a substrate having a magnetic tunneling junction (MTJ) region and a logic region; forming a MTJ on the MTJ region; forming a top electrode on the MTJ; forming an inter-metal dielectric (IMD) layer around the MTJ; removing the IMD layer directly on the top electrode to form a recess; forming a first hard mask on the IMD layer and into the recess; removing the first hard mask and the IMD layer on the logic region to form a contact hole; and forming a metal layer in the recess and the contact hole to form a connecting structure on the top electrode and a metal interconnection on the logic region.

公开(公告)号：US20210036053A1

公开(公告)日：2021-02-04

申请号：US17074643

申请日：2020-10-20

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hui-Lin Wang ,  Chia-Chang Hsu ,  Chen-Yi Weng ,  Hung-Chan Lin ,  Jing-Yin Jhang ,  Yu-Ping Wang

IPC: H01L27/22 ,  G11C11/16 ,  H01L23/48 ,  H01L43/12 ,  H01L23/544 ,  H01L21/321 ,  H01L21/762 ,  H01L23/485

Abstract: The disclosure provides a semiconductor memory device including a substrate having a memory cell region and an alignment mark region; a dielectric layer covering the memory cell region and the alignment mark region; conductive vias in the dielectric layer within the memory cell region; an alignment mark trench in the dielectric layer within the alignment mark region; and storage structures disposed on the conductive vias, respectively. Each of the storage structures includes a bottom electrode defined from a bottom electrode metal layer, a magnetic tunnel junction (MTJ) structure defined from an MTJ layer, and a top electrode. A residual metal stack is left in the alignment mark trench. The residual metal stack includes a portion of the bottom electrode metal layer and a portion of the MTJ layer.

公开(公告)号：US10727397B1

公开(公告)日：2020-07-28

申请号：US16261524

申请日：2019-01-29

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hui-Lin Wang ,  Yi-Wei Tseng ,  Meng-Jun Wang ,  Chen-Yi Weng ,  Chin-Yang Hsieh ,  Jing-Yin Jhang ,  Yu-Ping Wang ,  Chien-Ting Lin ,  Ying-Cheng Liu ,  Yi-An Shih ,  Yi-Hui Lee ,  I-Ming Tseng

IPC: H01L43/02 ,  H01L27/22 ,  H01L43/08 ,  H01L43/12 ,  H01L45/00 ,  H01L27/108 ,  H01L43/10

Abstract: A magneto-resistive random access memory (MRAM) cell includes a substrate having a dielectric layer disposed thereon, a conductive via disposed in the dielectric layer, and a cylindrical stack disposed on the conductive via. The cylindrical stack includes a bottom electrode, a magnetic tunneling junction (MTJ) layer on the bottom electrode, and a top electrode on the MTJ layer. A spacer layer is disposed on a sidewall of the cylindrical stack. The top electrode protrudes from a top surface of the spacer layer.

公开(公告)号：US10707412B2

公开(公告)日：2020-07-07

申请号：US16208566

申请日：2018-12-04

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chen-Yi Weng ,  Jing-Yin Jhang ,  Hui-Lin Wang ,  Chin-Yang Hsieh

IPC: H01L43/12 ,  H01L27/22 ,  H01L43/10 ,  H01L43/02 ,  H01L43/08

Abstract: A manufacturing method of a semiconductor device includes the following steps. A first inter-metal dielectric (IMD) layer is formed on a substrate. A cap layer is formed on the first IMD layer. A connection structure is formed on the substrate and penetrates the cap layer and the first IMD layer. A magnetic tunnel junction (MTJ) stack is formed on the connection structure and the cap layer. A patterning process is performed to the MTJ stack for forming a MTJ structure on the connection structure and removing the cap layer. A second IMD layer is formed on the first IMD layer and surrounds the MTJ structure. The semiconductor device includes the substrate, the connection structure, the first IMD layer, the MTJ structure, and the second IMD layer. The dielectric constant of the first IMD layer is lower than the dielectric constant of the second IMD layer.

公开(公告)号：US20160148816A1

公开(公告)日：2016-05-26

申请号：US14549529

申请日：2014-11-20

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Rung-Yuan Lee ,  Yu-Ting Li ,  Jing-Yin Jhang ,  Chen-Yi Weng ,  Jia-Feng Fang ,  Yi-Wei Chen ,  Wei-Jen Wu ,  Po-Cheng Huang ,  Fu-Shou Tsai ,  Kun-Ju Li ,  Wen-Chin Lin ,  Chih-Chien Liu ,  Chih-Hsun Lin ,  Chun-Yuan Wu

IPC: H01L21/306 ,  H01L21/28

CPC classification number: H01L21/30625 ,  H01L21/28123 ,  H01L21/32115 ,  H01L21/3212

Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate; forming a first material layer on the substrate; forming a stop layer on the first material layer; forming a second material layer on the stop layer; and performing a planarizing process to remove the second material layer, the stop layer, and part of the first material layer for forming a gate layer.

Abstract translation: 公开了半导体器件的制造方法。 该方法包括以下步骤：提供衬底; 在所述基板上形成第一材料层; 在所述第一材料层上形成停止层; 在所述停止层上形成第二材料层; 并且进行平面化处理以去除第二材料层，停止层以及用于形成栅极层的第一材料层的一部分。

公开(公告)号：US12232425B2

公开(公告)日：2025-02-18

申请号：US18515273

申请日：2023-11-21

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hui-Lin Wang ,  Si-Han Tsai ,  Dong-Ming Wu ,  Chen-Yi Weng ,  Ching-Hua Hsu ,  Ju-Chun Fan ,  Yi-Yu Lin ,  Che-Wei Chang ,  Po-Kai Hsu ,  Jing-Yin Jhang

IPC: G11C11/00 ,  G11C11/16 ,  H01F10/32 ,  H10B61/00 ,  H10N50/10 ,  H10N50/80 ,  H10N50/85

Abstract: A magnetoresistive random access memory (MRAM) device includes a first array region and a second array region on a substrate, a first magnetic tunneling junction (MTJ) on the first array region, a first top electrode on the first MTJ, a second MTJ on the second array region, and a second top electrode on the second MTJ. Preferably, the first top electrode and the second top electrode include different nitrogen to titanium (N/Ti) ratios.