公开(公告)号：US06567296B1

公开(公告)日：2003-05-20

申请号：US10041684

申请日：2001-10-24

申请人： Giulio Casagrande ,  Tyler Lowrey ,  Roberto Bez ,  Guy Wicker ,  Edward Spall ,  Stephen Hudgens ,  Wolodymyr Czubatyj

发明人： Giulio Casagrande ,  Tyler Lowrey ,  Roberto Bez ,  Guy Wicker ,  Edward Spall ,  Stephen Hudgens ,  Wolodymyr Czubatyj

IPC分类号： G11C1706

CPC分类号： G11C11/56 ,  G11C11/5678 ,  G11C13/0004 ,  G11C2213/72

摘要： A memory device including a plurality of memory cells, a plurality of insulated first regions of a first type of conductivity formed in a chip of semiconductor material, at least one second region of a second type of conductivity formed in each first region, a junction between each second region and the corresponding first region defining a unidirectional conduction access element for selecting a corresponding memory cell connected to the second region when forward biased, and at least one contact for contacting each first region; a plurality of access elements are formed in each first region, the access elements being grouped into at least one sub-set consisting of a plurality of adjacent access elements without interposition of any contact, and the memory device further includes means for forward biasing the access elements of each sub-set simultaneously.

摘要翻译： 一种存储器件，包括多个存储器单元，形成在半导体材料的芯片中的第一类型的导电性的多个绝缘的第一区域，在每个第一区域中形成的至少一个第二导电类型的第二区域， 每个第二区域和相应的第一区域限定单向传导访问元件，用于当正向偏置时选择连接到第二区域的对应的存储单元，以及用于接触每个第一区域的至少一个触点; 在每个第一区域中形成多个访问元件，所述访问元件被分组成由多个相邻的访问元件组成的至少一个子集，而不插入任何联系人，并且所述存储器设备还包括： 每个子集的元素同时进行。

公开(公告)号：US07110289B1

公开(公告)日：2006-09-19

申请号：US10816271

申请日：2004-03-31

申请人： Kyusik Sin ,  Hugh Craig Hiner ,  Xizeng (Stone) Shi ,  William D. Jensen ,  Hua-Ching Tong ,  Matthew R Gibbons ,  Roberto Bez ,  Giulio Casagrande ,  Paolo Cappeletti ,  Marco Pasotti

发明人： Kyusik Sin ,  Hugh Craig Hiner ,  Xizeng (Stone) Shi ,  William D. Jensen ,  Hua-Ching Tong ,  Matthew R Gibbons ,  Roberto Bez ,  Giulio Casagrande ,  Paolo Cappeletti ,  Marco Pasotti

IPC分类号： G11C11/15

CPC分类号： G11C11/15

摘要： In a method and system for reducing power consumed by a magnetic memory, magnetic memory cells are coupled to a bit line and are associated with a plurality of digit lines. A bit line current is provided in the bit line. Digit currents are provided in parallel in the digit lines at substantially the same time as the bit line current. The digit and bit line currents allow the magnetic memory cells to be written to a plurality of states in parallel.

摘要翻译： 在用于减少由磁存储器消耗的功率的方法和系统中，磁存储器单元耦合到位线并与多个数字线相关联。 位线中提供位线电流。 与位线电流基本相同的时刻，在数字线中并联提供数字电流。 数字和位线电流允许磁存储单元被并行写入多个状态。

公开(公告)号：US5576990A

公开(公告)日：1996-11-19

申请号：US367538

申请日：1995-01-03

申请人： Emilio Camerlenghi ,  Giulio Casagrande

发明人： Emilio Camerlenghi ,  Giulio Casagrande

IPC分类号： G11C17/00 ,  G11C5/14 ,  G11C16/06 ,  G11C16/30 ,  G11C11/34

CPC分类号： G11C5/147 ,  G11C16/30

摘要： A voltage regulator for electrically programmable non-volatile semiconductor memory devices of the type comprising a gain stage (3), supplied by a programming voltage (V.sub.PP) and having an input terminal connected to a divider (6) of said programming voltage (V.sub.PP) and an output terminal (U) connected to a programming line (5) of at least one memory cell (2) comprises at least one circuit element (4) capable of adapting the line programming voltage (5) to the length (L) of the memory cell (2). This solution makes it possible to have on the bit line of the memory device a drain voltage varying according to the actual length of the memory cell.

摘要翻译： 一种用于电可编程非易失性半导体存储器件的电压调节器，包括由编程电压（VPP）提供并具有连接到所述编程电压（VPP）的分压器（6）的输入端的增益级（3） 以及连接到至少一个存储单元（2）的编程线（5）的输出端（U）包括至少一个电路元件（4），其能够将线路编程电压（5）适应于 存储单元（2）。 该解决方案使得可以在存储器件的位线上具有根据存储器单元的实际长度而变化的漏极电压。

公开(公告)号：US4807188A

公开(公告)日：1989-02-21

申请号：US199077

申请日：1988-05-26

申请人： Giulio Casagrande

发明人： Giulio Casagrande

IPC分类号： G11C17/00 ,  G11C16/04 ,  G11C16/06 ,  G11C16/10 ,  G11C16/28 ,  G11C29/00 ,  G11C29/04 ,  H01L21/822 ,  H01L21/8246 ,  H01L21/8247 ,  H01L27/04 ,  H01L27/112 ,  H01L29/788 ,  H01L29/792 ,  G11C11/34 ,  G11C7/00 ,  H03K3/01

CPC分类号： G11C16/3495 ,  G11C16/0441 ,  G11C16/10 ,  G11C16/28

摘要： An electrically alterable, non volatile memory device capable of enduring a high number of cycles utilizes an array of "semidouble" cells, each formed by a pair of elementary EEPROM cells connected substantially in parallel and a single select transistor. A special program lines biasing circuit generating a bias voltage representative of a condition wherein one of the two elementary EEPROM structure is broken and sense amplifiers comprising a comparator circuit comparing the current flowing through an addressed semidouble memory cell with the current flowing through a reference cell comprising a pair of virgin EEPROM type elementary cells to ensure operability of each bit of the memory also when one of the two elementary cells supporting the bit fails. Different from known memories, only the EEPROM structure is duplicated while column lines, select lines and ancillary circuitry don't require duplication.

公开(公告)号：US20070099347A1

公开(公告)日：2007-05-03

申请号：US11551170

申请日：2006-10-19

申请人： Fabio Pellizzer ,  Giulio Casagrande ,  Roberto Bez

发明人： Fabio Pellizzer ,  Giulio Casagrande ,  Roberto Bez

IPC分类号： H01L21/00

CPC分类号： H01L27/2445 ,  H01L27/101 ,  H01L27/2463 ,  H01L29/685 ,  H01L45/06 ,  H01L45/1233

摘要： A cell array is formed by a plurality of cells each including a selection bipolar transistor and a storage component. The cell array is formed in a body including a common collector region of P type; a plurality of base regions of N type, overlying the common collector region; a plurality of emitter regions of P type formed in the base regions; and a plurality of base contact regions of N type and a higher doping level than the base regions, formed in the base regions, wherein each base region is shared by at least two adjacent bipolar transistors.

摘要翻译： 单元阵列由多个单元形成，每个单元包括选择双极晶体管和存储组件。 电池阵列形成在包括P型共用集电极区域的主体中; 多个N型基极区，覆盖在公共集电极区域上; 在基区中形成多个P型发射极区; 以及形成在所述基极区域中的多个N型基极接触区域和比所述基极区域更高的掺杂水平的基极接触区域，其中每个基极区域由至少两个相邻的双极晶体管共享。

公开(公告)号：US07012832B1

公开(公告)日：2006-03-14

申请号：US10698747

申请日：2003-10-31

申请人： Kyusik Sin ,  Matthew R. Gibbons ,  William D. Jensen ,  Hugh Craig Hiner ,  Xizeng Stone Shi ,  Roberto Bez ,  Giulio Casagrande ,  Paolo Cappelletti

发明人： Kyusik Sin ,  Matthew R. Gibbons ,  William D. Jensen ,  Hugh Craig Hiner ,  Xizeng Stone Shi ,  Roberto Bez ,  Giulio Casagrande ,  Paolo Cappelletti

IPC分类号： G11C11/00

CPC分类号： G11C11/16

摘要： A magnetic random access memory (MRAM) device has increased ΔR/R for sensing a state of a pin-dependent tunneling (SDT) device. The MRAM device includes plural transistors connected to a read line for sensing the state of the SDT device. Plural transistors lower an underlying resistance during reading, increasing ΔR/R. The plural transistors can share a source region.

摘要翻译： 磁性随机存取存储器（MRAM）器件增加了用于感测引脚依赖隧道（SDT）器件的状态的DeltaR / R。 MRAM器件包括连接到读取线的多个晶体管，用于感测SDT器件的状态。 多个晶体管在读取期间降低潜在电阻，增加DeltaR / R。 多个晶体管可以共享源极区域。

公开(公告)号：US5905677A

公开(公告)日：1999-05-18

申请号：US831046

申请日：1997-04-01

申请人： Giulio Casagrande ,  Emilio Camerlenghi

发明人： Giulio Casagrande ,  Emilio Camerlenghi

IPC分类号： G11C17/00 ,  G11C5/14 ,  G11C16/06 ,  G11C16/30 ,  G11C13/00

CPC分类号： G11C16/30 ,  G11C5/147

摘要： A voltage regulator for electrically programmable non-volatile semiconductor memory devices of the type comprising a gain stage (3), supplied by a programming voltage (Vpp) and having an input terminal connected to a divider (6) of said programming voltage (Vpp) and an output terminal (U) connected to a programming line (5) of at least one memory cell (2) comprises at least one circuit element (4) capable of adapting the line programming voltage (5) to the length (L) of the memory cell (2). This provides a drain voltage, on the bit line of the memory device, which varies according to the actual length of the memory cell.

摘要翻译： 一种用于电可编程非易失性半导体存储器件的电压调节器，包括由编程电压（Vpp）提供并具有连接到所述编程电压（Vpp）的分压器（6）的输入端的增益级（3） 以及连接到至少一个存储单元（2）的编程线（5）的输出端（U）包括至少一个电路元件（4），其能够将线路编程电压（5）适应于 存储单元（2）。 这提供了存储器件的位线上的漏极电压，其根据存储器单元的实际长度而变化。