公开(公告)号：US07948814B2

公开(公告)日：2011-05-24

申请号：US12164797

申请日：2008-06-30

申请人： Dae-Han Kwon ,  Kyung-Hoon Kim ,  Taek-Sang Song

发明人： Dae-Han Kwon ,  Kyung-Hoon Kim ,  Taek-Sang Song

IPC分类号： G11C7/00

CPC分类号： G11C7/22 ,  G11C7/222 ,  G11C7/225

摘要： A semiconductor memory device including a clock input for receiving a source clock and supplying a generated clock to a plurality of clock transmission lines; a plurality of clock amplifiers, each amplifying a respective generated clock loaded on one of the plurality of clock transmission lines in response to a column enable signal; and a data input/output for inputting/outputting a plurality of data in response to the amplified clocks output by the plurality of clock amplifiers.

摘要翻译： 一种半导体存储器件，包括用于接收源时钟并将产生的时钟提供给多个时钟传输线的时钟输入; 多个时钟放大器，每个时钟放大器响应于列使能信号放大加载在所述多个时钟传输线中的一个上的相应的生成时钟; 以及用于响应于由多个时钟放大器输出的放大时钟而输入/输出多个数据的数据输入/输出。

公开(公告)号：US07863955B2

公开(公告)日：2011-01-04

申请号：US12005564

申请日：2007-12-27

申请人： Dae-Han Kwon ,  Kyung-Hoon Kim ,  Dae-Kun Yoon ,  Taek-Sang Song

发明人： Dae-Han Kwon ,  Kyung-Hoon Kim ,  Dae-Kun Yoon ,  Taek-Sang Song

IPC分类号： H03K3/017

CPC分类号： H03K5/1565

摘要： A semiconductor device includes a pulse signal generating unit for generating a plurality of pulse signals each of which has a different pulse width from each other, a signal multiplexing unit for outputting one of the plurality of the pulse signals as an enable signal in response to frequencies of external clock signals, and a duty ratio detecting unit for detecting a duty ratio of the external clock signals in response to the enable signal.

摘要翻译： 一种半导体器件包括：脉冲信号产生单元，用于产生彼此具有不同脉冲宽度的多个脉冲信号;信号复用单元，用于响应于频率输出多个脉冲信号中的一个作为使能信号 以及占空比检测单元，用于响应于使能信号检测外部时钟信号的占空比。

公开(公告)号：US07768307B2

公开(公告)日：2010-08-03

申请号：US12005443

申请日：2007-12-26

申请人： Kyung-Hoon Kim ,  Dae-Han Kwon

发明人： Kyung-Hoon Kim ,  Dae-Han Kwon

IPC分类号： H03K19/0175

CPC分类号： H03K19/018521 ,  H03K19/0948

摘要： A current mode logic (CML)-complementary metal oxide semiconductor (CMOS) converter prevents change of a duty ratio to stably operate during an operation for converting a CML level signal into a CMOS level signal. The CML-CMOS converter includes a reference level shifting unit configured to receive a CML signal swinging about a first reference level to shift a swing reference level to a second reference level; and an amplifying unit configured to amplify an output signal of the reference level shifting unit to output the amplified signal as a CMOS signal.

摘要翻译： 电流模式逻辑（CML） - 互补金属氧化物半导体（CMOS）转换器在用于将CML电平信号转换为CMOS电平信号的操作期间防止占空比的变化以稳定地操作。 CML-CMOS转换器包括参考电平移位单元，被配置为接收围绕第一参考电平摆动的CML信号，以将摆幅参考电平移位到第二参考电平; 以及放大单元，被配置为放大参考电平移位单元的输出信号以输出放大的信号作为CMOS信号。

公开(公告)号：US07738621B2

公开(公告)日：2010-06-15

申请号：US12005933

申请日：2007-12-28

申请人： Dae-Kun Yoon ,  Kyung-Hoon Kim ,  Dae-Han Kwon ,  Taek-Sang Song

发明人： Dae-Kun Yoon ,  Kyung-Hoon Kim ,  Dae-Han Kwon ,  Taek-Sang Song

IPC分类号： G06M3/00 ,  H03K21/40

CPC分类号： G06M3/12

摘要： A counter with overflow prevention capability includes a counting unit configured to count an output code in response to an input signal and an overflow preventing unit configured to control the counting unit to stop counting the output code when a current value of the output code is a maximum value but a previous value thereof is not the maximum value.

摘要翻译： 具有防溢能力的计数器包括：计数单元，被配置为响应于输入信号对输出代码进行计数;以及溢出防止单元，被配置为当输出代码的当前值为最大值时，控制计数单元停止计数输出代码 值，但其前一值不是最大值。

公开(公告)号：US07696831B2

公开(公告)日：2010-04-13

申请号：US12079443

申请日：2008-03-26

申请人： Taek-Sang Song ,  Kyung-Hoon Kim ,  Dae-Han Kwon

发明人： Taek-Sang Song ,  Kyung-Hoon Kim ,  Dae-Han Kwon

IPC分类号： H03L7/085 ,  H03L7/089

CPC分类号： H03L7/0893 ,  H03L7/0896 ,  H03L7/0898

摘要： Phase locked loop and method for controlling the same includes a phase/frequency detector configured to detect a phase difference between an input clock and a feedback clock to generate an up signal or a down signal depending on the detected phase difference, a charge pump configured to variably control a bandwidth according to a bandwidth control signal input thereinto, the charge pump operating in response to the up signal or the down signal and a voltage controlled oscillator configured to change a frequency according to an output of the charge pump.

摘要翻译： 锁相环及其控制方法包括相位/频率检测器，被配置为检测输入时钟和反馈时钟之间的相位差，以根据检测到的相位差产生上升信号或下降信号，电荷泵被配置为 根据其中输入的带宽控制信号可变地控制带宽，所述电荷泵响应于上升信号或下降信号而工作;以及压控振荡器，被配置为根据电荷泵的输出来改变频率。

公开(公告)号：US20100061157A1

公开(公告)日：2010-03-11

申请号：US12327397

申请日：2008-12-03

申请人： Jun-woo Lee ,  Dae-Han Kwon ,  Taek-Sang Song

发明人： Jun-woo Lee ,  Dae-Han Kwon ,  Taek-Sang Song

IPC分类号： G11C7/00 ,  G11C8/18 ,  G11C5/14

CPC分类号： G11C7/02 ,  G11C7/1006 ,  G11C7/1051 ,  G11C7/1066 ,  G11C7/22 ,  G11C8/18 ,  G11C11/4076 ,  G11C11/4096 ,  G11C2207/107

摘要： A data output circuit includes a serial data output unit for outputting a plurality of parallel data as serial data according to an operation mode, an internal information output unit for outputting internal information data according to the operation mode, and a buffering unit for receiving the serial data and the internal information data through an identical input end and buffering the received data.

摘要翻译： 数据输出电路包括：串行数据输出单元，用于根据操作模式输出多个并行数据作为串行数据;内部信息输出单元，用于根据操作模式输出内部信息数据;以及缓冲单元，用于接收串行数据 数据和内部信息数据通过相同的输入端并缓冲接收到的数据。

公开(公告)号：US20100013535A1

公开(公告)日：2010-01-21

申请号：US12344642

申请日：2008-12-29

申请人： Taek-Sang Song ,  Dae-Han Kwon ,  Jun-Woo Lee

发明人： Taek-Sang Song ,  Dae-Han Kwon ,  Jun-Woo Lee

IPC分类号： H03K3/00

CPC分类号： H03K3/356139 ,  H03K21/023

摘要： A latch circuit includes a data input/output unit configured to form a current path through a first node in response to an input data to output an output data, a holding unit configured to form a current path through a second node in response to the output data to store the output data, and a clock input unit coupled to the first and second nodes in parallel in response to a clock.

摘要翻译： 锁存电路包括：数据输入/输出单元，被配置为响应于输入数据形成通过第一节点的电流路径以输出输出数据;保持单元，被配置为响应于输出形成通过第二节点的电流路径 用于存储输出数据的数据，以及响应于时钟并行耦合到第一和第二节点的时钟输入单元。

公开(公告)号：US20090278577A1

公开(公告)日：2009-11-12

申请号：US12164758

申请日：2008-06-30

申请人： Dae-Kun Yoon ,  Dae-Han Kwon ,  Chang-Kyu Choi ,  Jun-Woo Lee

发明人： Dae-Kun Yoon ,  Dae-Han Kwon ,  Chang-Kyu Choi ,  Jun-Woo Lee

IPC分类号： H03L7/06

CPC分类号： H03L7/0814 ,  H03K3/356121 ,  H03K3/356182

摘要： A semiconductor device including an edge synchronizer which outputs a synchronized strobe signal generated by synchronizing a transition time point of a strobe signal with clock edges of a main clock or a sub clock, a detector which outputs a phase determination signal indicating a phase difference between the main clock and the sub clock in response to the synchronized strobe signal, and a duty ratio corrector which adjusts a duty ratio of the main clock and the sub clock in response to the phase determination signal.

摘要翻译： 一种半导体器件，包括边沿同步器，其输出通过使选通信号的转变时间点与主时钟或子时钟的时钟沿同步而产生的同步选通信号;输出相位确定信号的检测器， 主时钟和子时钟响应于同步选通信号;以及占空比校正器，其响应于相位确定信号调整主时钟和子时钟的占空比。

公开(公告)号：US20090167441A1

公开(公告)日：2009-07-02

申请号：US12217049

申请日：2008-06-30

申请人： Taek-Sang Song ,  Kyung-Hoon Kim ,  Dae-Han Kwon

发明人： Taek-Sang Song ,  Kyung-Hoon Kim ,  Dae-Han Kwon

IPC分类号： H03L7/00 ,  H03L7/24

CPC分类号： H03L7/0812 ,  H03L7/18 ,  H03L7/24

摘要： An injection locking clock generator can vary the free running frequency of an injection locking oscillator to broaden an operating frequency range of an oscillation signal injected to itself, thereby performing an injection locking with respect to all frequencies of an operating frequency range. The clock generator includes a main oscillator configured to generate oscillation signals of a frequency corresponding to a control voltage, and an injection locking oscillator configured to generate division signals synchronized with the oscillation signals by dividing the oscillation signals, wherein a free running frequency of the injection locking oscillator is set according to the frequency of the oscillation signals.

摘要翻译： 注入锁定时钟发生器可以改变注入锁定振荡器的自由运行频率，以扩大注入到其自身的振荡信号的工作频率范围，从而相对于工作频率范围的所有频率执行注入锁定。 时钟发生器包括：主振荡器，其被配置为产生与控制电压对应的频率的振荡信号;以及注入锁定振荡器，其被配置为通过划分所述振荡信号产生与所述振荡信号同步的除法信号，其中所述注入的自由运行频率 锁定振荡器根据振荡信号的频率设定。

公开(公告)号：US20080238502A1

公开(公告)日：2008-10-02

申请号：US12003676

申请日：2007-12-31

申请人： Taek-Sang Song ,  Kyung-Hoon Kim ,  Dae-Han Kwon

发明人： Taek-Sang Song ,  Kyung-Hoon Kim ,  Dae-Han Kwon

IPC分类号： H03L7/08 ,  H03H11/26

CPC分类号： H03L7/0995 ,  H03K3/0322 ,  H03K5/133 ,  H03K2005/00208 ,  H03K2005/00234 ,  H03L2207/06

摘要： A phase locked loop that generates an internal clock by controlling a delay time of a delay cell according to conditions of PVT, thereby improving a jitter characteristic of the internal clock. The delay cell includes a first current controller for controlling first and second currents in response to a control voltage, and a second current controller for controlling the first and second currents in response to frequency range selection signals. The phase locked loop includes a phase comparator for comparing a reference clock with a feedback clock, a control voltage generator for generating a control voltage corresponding to an output of the phase comparator, and a voltage controlled oscillator for generating an internal clock having a frequency in response to the control voltage and one or more frequency range control signals, wherein the feedback clock is generated using the internal clock.

摘要翻译： 通过根据PVT的条件控制延迟单元的延迟时间来产生内部时钟的锁相环，从而提高内部时钟的抖动特性。 延迟单元包括响应于控制电压控制第一和第二电流的第一电流控制器，以及响应频率范围选择信号控制第一和第二电流的第二电流控制器。 锁相环包括用于将参考时钟与反馈时钟进行比较的相位比较器，用于产生对应于相位比较器的输出的控制电压的控制电压发生器和用于产生具有频率的内部时钟的压控振荡器 响应于控制电压和一个或多个频率范围控制信号，其中使用内部时钟产生反馈时钟。