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    Method of fabrication of semiconductor integrated circuit device
    33.
    发明授权
    Method of fabrication of semiconductor integrated circuit device 失效
    半导体集成电路器件制造方法

    公开(公告)号：US5610089A

    公开(公告)日：1997-03-11

    申请号：US429868

    申请日：1995-04-27

    申请人： Hidetoshi Iwai ,  Kazumichi Mitsusada ,  Masamichi Ishihara ,  Tetsuro Matsumoto ,  Kazuyuki Miyazawa ,  Hisao Katto ,  Kousuke Okuyama

    发明人： Hidetoshi Iwai ,  Kazumichi Mitsusada ,  Masamichi Ishihara ,  Tetsuro Matsumoto ,  Kazuyuki Miyazawa ,  Hisao Katto ,  Kousuke Okuyama

    IPC分类号： H01L21/8238 ,  H01L21/8242 ,  H01L27/02 ,  H01L27/092 ,  H01L29/78

    CPC分类号： H01L27/10873 ,  H01L21/823864 ,  H01L27/0251 ,  H01L27/0266 ,  H01L27/0922 ,  H01L29/78 ,  H01L29/7836

    摘要： Disclosed is a semiconductor device having an internal circuit protected by an electrostatic protective circuit, the internal circuit and electrostatic protective circuit being formed on the same semiconductor substrate. The internal circuit includes MIS elements and has a double-diffused drain structure, while the protective circuit has a single-diffused drain structure. The internal circuit can be, e.g., a DRAM, and the protective circuit can have diffused resistors and clamping MIS elements. The single-diffused drain structure can be formed in the protective circuit on the semiconductor substrate, while providing double-diffused drain structure in the internal circuit on the same substrate, by: (1) scanning the ion implanting apparatus to avoid ion implantation of the first ions into the region of the protective circuit, and/or (2) forming a photoresist film over the region of the protective circuit to prevent ion implanation of the first ions into the protective circuit region. As a further embodiment of the present invention, a semiconductor integrated circuit device is provided wherein the source and drain regions of an MOSFET in the internal circuit have lightly doped drain (LDD) structure in order to suppress the appearance of hot carriers, and the source and drain regions of an MOSFET in the input/output circuit have structure doped with phosphorus at a high impurity concentration, in order to enhance an electrostatic breakdown voltage.

    摘要翻译： 公开了具有被静电保护电路保护的内部电路的半导体器件，内部电路和静电保护电路形成在同一半导体衬底上。 内部电路包括MIS元件，并具有双扩散漏极结构，而保护电路具有单扩散漏极结构。 内部电路可以是例如DRAM，并且保护电路可以具有扩散电阻器和钳位MIS元件。 单扩散漏极结构可以形成在半导体衬底上的保护电路中，同时通过以下步骤在同一衬底上的内部电路中提供双扩散漏极结构：（1）扫描离子注入装置以避免离子注入 第一离子进入保护电路的区域，和/或（2）在保护电路的区域上形成光致抗蚀剂膜，以防止第一离子离子注入保护电路区域。 作为本发明的另一实施例，提供了一种半导体集成电路器件，其中内部电路中的MOSFET的源极和漏极区域具有轻掺杂漏极（LDD）结构，以便抑制热载流子的出现，源极 并且输入/输出电路中的MOSFET的漏极区域掺杂有高杂质浓度的磷的结构，以增强静电击穿电压。

    Method of making mask pattern data and process for manufacturing the mask
    34.
    发明授权
    Method of making mask pattern data and process for manufacturing the mask 失效
    制作掩模图案数据的方法和用于制造掩模的工艺

    公开(公告)号：US5565285A

    公开(公告)日：1996-10-15

    申请号：US534829

    申请日：1995-09-27

    申请人： Toshitsugu Takekuma ,  Toshio Suzuki ,  Hidetoshi Iwai ,  Masamichi Ishihara

    发明人： Toshitsugu Takekuma ,  Toshio Suzuki ,  Hidetoshi Iwai ,  Masamichi Ishihara

    IPC分类号： G03F1/00 ,  G03F1/26 ,  G03F1/30 ,  G03F1/36 ,  G03F1/68 ,  G03F1/84 ,  H01L21/027 ,  H01L21/30 ,  G03F9/00

    CPC分类号： G03F1/26 ,  G03F1/29 ,  G03F1/84

    摘要： Pattern data of a phase shift mask can be inspected: (101) by separating and laying out pattern data of a phase shift mask in an actual pattern data layer, an auxiliary pattern data layer and a phase shift pattern data layer; (102) by inspecting and correcting only the data of the actual pattern of the actual pattern data layer; (103) by making data of an estimated pattern estimated to be transferred to a semiconductor wafer from the data of the synthetic data of the correct actual pattern data, the auxiliary pattern data and the phase shift pattern data, which are inspected and corrected; and (104) by comparing the estimated pattern data and the actual pattern data to inspect the data of the auxiliary pattern and the phase shift pattern.

    摘要翻译： 可以检查相移掩模的图案数据：（101）通过在实际图案数据层，辅助图案数据层和相移图案数据层中分离和布置相移掩模的图案数据; （102），通过检查和校正实际图案数据层的实际图案的数据; （103）通过从被检查和校正的正确实际图案数据，辅助图案数据和相移图案数据的合成数据的数据中制作估计传送到半导体晶片的估计图案的数据; 和（104）通过比较估计的图案数据和实际图案数据来检查辅助图案和相移图案的数据。

    Semiconductor integrated circuit device having output and internal circuit MISFETS
    35.
    发明授权
    Semiconductor integrated circuit device having output and internal circuit MISFETS 失效
    具有输出和内部电路MISFETS的半导体集成电路器件

    公开(公告)号：US5534723A

    公开(公告)日：1996-07-09

    申请号：US431568

    申请日：1995-04-27

    申请人： Hidetoshi Iwai ,  Kazumichi Mitsusada ,  Masamichi Ishihara ,  Tetsuro Matsumoto ,  Kazuyuki Miyazawa ,  Hisao Katto ,  Kousuke Okuyama

    发明人： Hidetoshi Iwai ,  Kazumichi Mitsusada ,  Masamichi Ishihara ,  Tetsuro Matsumoto ,  Kazuyuki Miyazawa ,  Hisao Katto ,  Kousuke Okuyama

    IPC分类号： H01L21/8238 ,  H01L21/8242 ,  H01L27/02 ,  H01L27/092 ,  H01L29/78 ,  H01L29/06

    CPC分类号： H01L21/823864 ,  H01L27/0251 ,  H01L27/0266 ,  H01L27/0922 ,  H01L27/10873 ,  H01L29/78

    摘要： Disclosed is a semiconductor device having an internal circuit protected by an electrostatic protective circuit, the internal circuit and electrostatic protective circuit being formed on the same semiconductor substrate. The internal circuit includes MIS elements and has a double-diffused drain structure, while the protective circuit has a single-diffused drain structure. The internal circuit can be, e.g., a DRAM, and the protective circuit can have diffused resistors and clamping MIS elements. The single-diffused drain structure can be formed in the protective circuit on the semiconductor substrate, while providing double-diffused drain structure in the internal circuit on the same substrate, by: (1) scanning the ion implanting apparatus to avoid ion implantation of the first ions into the region of the protective circuit, and/or (2) forming a photoresist film over the region of the protective circuit to prevent ion implantation of the first ions into the protective circuit region. As a further embodiment of the present invention, a semiconductor integrated circuit device is provided wherein the source and drain regions of an MOSFET in the internal circuit have lightly doped drain (LDD) structure in order to suppress the appearance of hot carriers, and the source and drain regions of an MOSFET in the input/output circuit have structure doped with phosphorus at a high impurity concentration, in order to enhance an electrostatic breakdown voltage.

    摘要翻译： 公开了具有被静电保护电路保护的内部电路的半导体器件，内部电路和静电保护电路形成在同一半导体衬底上。 内部电路包括MIS元件，并具有双扩散漏极结构，而保护电路具有单扩散漏极结构。 内部电路可以是例如DRAM，并且保护电路可以具有扩散电阻器和钳位MIS元件。 单扩散漏极结构可以形成在半导体衬底上的保护电路中，同时通过以下步骤在同一衬底上的内部电路中提供双扩散漏极结构：（1）扫描离子注入装置以避免离子注入 第一离子进入保护电路的区域，和/或（2）在保护电路的区域上形成光致抗蚀剂膜，以防止第一离子离子注入保护电路区域。 作为本发明的另一实施例，提供了一种半导体集成电路器件，其中内部电路中的MOSFET的源极和漏极区域具有轻掺杂漏极（LDD）结构，以便抑制热载流子的出现，源极 并且输入/输出电路中的MOSFET的漏极区域掺杂有高杂质浓度的磷的结构，以增强静电击穿电压。

    Transistor layout for semiconductor integrated circuit
    36.
    发明授权
    Transistor layout for semiconductor integrated circuit 失效
    半导体集成电路晶体管布局

    公开(公告)号：US5498897A

    公开(公告)日：1996-03-12

    申请号：US270085

    申请日：1994-07-01

    申请人： Katsuo Komatsuzaki ,  Masayasu Kawamura ,  Hidetoshi Iwai

    发明人： Katsuo Komatsuzaki ,  Masayasu Kawamura ,  Hidetoshi Iwai

    IPC分类号： H01L27/105 ,  H01L27/11 ,  H01L29/772

    CPC分类号： H01L27/105 ,  Y10S257/927

    摘要： A semiconductor integrated circuit comprising a MOSFET having a metal wiring layer formed via an insulating film above and along the gate electrode of the MOSFET. The MOSFET is structured such that its channel length is small or channel width is large, and an input signal is applied from at least both end sides of the gate electrode thereof. Since the metal wiring layer for the input signal is formed on the gate electrode of the MOSFET, high-speed operation is possible without increasing the layout area. FIG. 1.

    摘要翻译： 一种半导体集成电路，包括具有金属布线层的MOSFET，所述金属布线层经由MOSFET上方并沿着栅极电极的绝缘膜形成。 MOSFET的结构使得其沟道长度小或沟道宽度大，并且从其栅电极的至少两端侧施加输入信号。 由于用于输入信号的金属布线层形成在MOSFET的栅电极上，因此可以在不增加布局面积的情况下进行高速运算。 图。 1。

    Semiconductor integrated device and wiring correction arrangement therefor
    37.
    发明授权
    Semiconductor integrated device and wiring correction arrangement therefor 失效
    半导体集成器件及其布线校正装置

    公开(公告)号：US5483490A

    公开(公告)日：1996-01-09

    申请号：US159619

    申请日：1993-12-01

    申请人： Hidetoshi Iwai ,  Masamichi Ishihara ,  Kazuya Ito ,  Wataru Arakawa ,  Yoshinobu Nakagome

    发明人： Hidetoshi Iwai ,  Masamichi Ishihara ,  Kazuya Ito ,  Wataru Arakawa ,  Yoshinobu Nakagome

    IPC分类号： G11C11/401 ,  G06F11/20 ,  G11C11/409 ,  G11C29/00 ,  G11C29/04 ,  H01L21/768 ,  H01L21/82 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108 ,  G11C13/00

    CPC分类号： H01L21/76894 ,  G11C29/83 ,  G11C29/832 ,  H01L21/76888 ,  G11C8/16

    摘要： An arrangement is provided for preventing DC defects in a memory or logic device after switching to a redundant circuit, improving the product yield of the device by cutting a leakage current path through a defective element or circuit. The cutting points formed by the predetermined wirings as a whole or a part thereof are provided to the device. A probe test of the formed chip is executed under the wafer condition by predetermined test equipment, and wiring correction data regarding the cutting of the cutting points is generated based on the result of test. Moreover, this wiring correction data is transmitted in an on-line fashion to the wiring correction equipment so that the corresponding cutting points can be cut. The wiring correction equipment can be formed by an EB direct writing apparatus, an FIB apparatus or a laser repair apparatus. With this arrangement, the leakage current path formed by a defective element or circuit left unused in conventional circuits is cut, and the product yield of the device is raised significantly. This arrangement can be used for a variety of memory or logic devices, including DRAMs, SRAMs, multiport memories and gate arrays.

    摘要翻译： 提供一种用于在切换到冗余电路之后防止存储器或逻辑器件中的DC缺陷的布置，通过切断通过故障元件或电路的漏电流路径来提高器件的产品产量。 由该预定布线整体形成的切割点或其一部分设置在该装置上。 通过预定的测试设备在晶片状态下执行形成的芯片的探针测试，并且基于测试结果产生关于切割点的切割的布线校正数据。 此外，该布线校正数据以线上方式发送到布线校正设备，使得可以切割相应的切割点。 布线校正装置可以由EB直接书写装置，FIB装置或激光修复装置形成。 利用这种布置，切割由常规电路中未使用的缺陷元件或电路形成的漏电流路径，并且显着提高器件的产品产量。 这种布置可以用于各种存储器或逻辑器件，包括DRAM，SRAM，多端口存储器和门阵列。

    Semiconductor storage device with redundancy arrangement
    38.
    发明授权
    Semiconductor storage device with redundancy arrangement 失效
    具有冗余布置的半导体存储设备

    公开(公告)号：US5047983A

    公开(公告)日：1991-09-10

    申请号：US586399

    申请日：1990-09-20

    申请人： Hidetoshi Iwai ,  Kazuyuki Miyazawa

    发明人： Hidetoshi Iwai ,  Kazuyuki Miyazawa

    IPC分类号： G06F11/16 ,  G11C11/401 ,  G11C29/00 ,  G11C29/04

    CPC分类号： G11C29/842

    摘要： In a semiconductor storage device having a spare memory, an input address signal is checked by an address comparator circuit. When the input address signal indicates an address which is to be relieved, the spare memory is selected instead of a memory array on the basis of the output of the address comparator circuit at that time. In conventional system, the access time of the semiconductor memory is restricted substantially by the operating time of the address comparator circuit during this operation. Accordingly, for enabling a quick access of the semiconductor memory, an address signal to be supplied to the address comparator circuit is output from a proceeding stage circuit of a plurality of amplification stages which form an address buffer circuit.

    摘要翻译： 在具有备用存储器的半导体存储装置中，由地址比较器电路检查输入地址信号。 当输入地址信号指示要被释放的地址时，基于当时的地址比较器电路的输出，选择备用存储器而不是存储器阵列。 在常规系统中，半导体存储器的访问时间基本上受到地址比较器电路在此操作期间的操作时间的限制。 因此，为了能够快速访问半导体存储器，从地址比较器电路提供的地址信号从形成地址缓冲电路的多个放大级的前级电路输出。