公开(公告)号：US06458639B1

公开(公告)日：2002-10-01

申请号：US09773828

申请日：2001-01-31

申请人： Judy Xilin An ,  Bin Yu ,  Ming-Ren Lin

发明人： Judy Xilin An ,  Bin Yu ,  Ming-Ren Lin

IPC分类号： H01L2974

CPC分类号： H01L21/28194 ,  H01L29/42368 ,  H01L29/513 ,  H01L29/518 ,  H01L29/66545 ,  H01L2924/0002 ,  Y10S257/90 ,  Y10S438/981 ,  H01L2924/00

摘要： A field effect transistor (FET) is formed on a silicon substrate, with a nitride gate insulator layer being deposited on the substrate and an oxide gate insulator layer being deposited on the nitride layer to insulate a gate electrode from source and drain regions in the substrate. The gate material is then removed to establish a gate void, and spacers are deposited on the sides of the void such that only a portion of the oxide layer is covered by the spacers. Then, the unshielded portion of the oxide layer is removed, thus establishing a step between the oxide and nitride layers that overlays the source and drain extensions under the gate void to reduce subsequent capacitive coupling and charge carrier tunneling between the gate and the extensions. The spacers are removed and the gate void is refilled with gate electrode material.

摘要翻译： 在硅衬底上形成场效应晶体管（FET），其中氮化物栅极绝缘体层沉积在衬底上，并且氧化物栅极绝缘体层沉积在氮化物层上以使栅电极与衬底中的源极和漏极区域绝缘 。 然后去除栅极材料以建立栅极空隙，并且间隔物沉积在空隙的侧面上，使得只有一部分氧化物层被间隔物覆盖。 然后，去除氧化物层的非屏蔽部分，从而在栅极空隙下的源极和漏极延伸层之间建立氧化物层和氮化物层之间的步骤，以减少栅极和延伸部之间的后续电容耦合和电荷载流子隧道。 去除间隔物，并用栅电极材料重新填充栅极空隙。

公开(公告)号：US06445016B1

公开(公告)日：2002-09-03

申请号：US09795159

申请日：2001-02-28

申请人： Judy Xilin An ,  Bin Yu

发明人： Judy Xilin An ,  Bin Yu

IPC分类号： H01L31072

CPC分类号： H01L29/66742 ,  H01L29/78618 ,  H01L29/78684

摘要： A silicon-on-insulator (SOI) transistor. The SOI transistor having a source and a drain having a body disposed therebetween, the source being implanted with germanium to form an area of silicon-germanium adjacent a source/body junction in a lower portion of the source, the area of silicon-germanium in the source forming a hetero junction along a lower portion of the source/body junction.

摘要翻译： 绝缘体上硅（SOI）晶体管。 具有源极和漏极的SOI晶体管具有设置在其间的主体，源被注入锗以形成邻近源极的下部的源极/主体结的硅 - 锗的区域，硅 - 锗的面积 源沿着源极/主体结的下部形成异质结。

公开(公告)号：US06410371B1

公开(公告)日：2002-06-25

申请号：US09794884

申请日：2001-02-26

申请人： Bin Yu ,  William G. En ,  Judy Xilin An ,  Concetta E. Riccobene

发明人： Bin Yu ,  William G. En ,  Judy Xilin An ,  Concetta E. Riccobene

IPC分类号： H01L2184

CPC分类号： H01L29/66742 ,  H01L21/76256 ,  H01L29/1054 ,  H01L29/78687 ,  Y10S438/977

摘要： A method of forming a semiconductor-on-insulator (SOI) wafer. The method includes the steps of providing a first wafer, the first wafer having a silicon substrate and an oxide layer disposed thereon; providing a second wafer, the second wafer having a silicon substrate, the substrate of the second wafer having a silicon-germanium layer disposed thereon, a silicon layer disposed on the silicon-germanium layer and an oxide layer disposed on the silicon layer; wafer bonding the first and second wafers; and removing an undesired portion of the substrate from the second wafer to form an upper silicon layer. The resulting SOI wafer structure is also disclosed.

摘要翻译： 一种形成绝缘体上半导体（SOI）晶片的方法。 该方法包括提供第一晶片，第一晶片具有硅衬底和设置在其上的氧化物层的步骤; 提供第二晶片，所述第二晶片具有硅衬底，所述第二晶片的衬底具有设置在其上的硅 - 锗层，设置在所述硅 - 锗层上的硅层和设置在所述硅层上的氧化物层; 晶片接合第一和第二晶片; 以及从所述第二晶片去除所述衬底的不希望的部分以形成上硅层。 还公开了所得到的SOI晶片结构。

公开(公告)号：US06187642B1

公开(公告)日：2001-02-13

申请号：US09334119

申请日：1999-06-15

申请人： Bin Yu ,  Judy Xilin An

发明人： Bin Yu ,  Judy Xilin An

IPC分类号： H01L21336

CPC分类号： H01L29/7834 ,  B01J2219/00315 ,  B01J2219/00317 ,  B01J2219/00527 ,  B01J2219/00585 ,  B01J2219/0059 ,  B01J2219/00596 ,  B01J2219/00605 ,  B01J2219/00653 ,  B01J2219/00659 ,  B01J2219/00686 ,  B01J2219/00689 ,  B01J2219/00713 ,  B01J2219/0072 ,  B01J2219/00722 ,  B01J2219/00725 ,  B01J2219/00731 ,  B82Y5/00 ,  B82Y10/00 ,  C07B2200/11 ,  C07H21/00 ,  C40B40/06 ,  C40B40/10 ,  C40B40/12 ,  C40B60/14 ,  G11C13/0014 ,  G11C13/0019 ,  G11C13/04 ,  G11C19/00 ,  H01L25/50 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66628 ,  H01L2924/0002 ,  H01L2924/00

摘要： The inventive method provides improved semiconductor devices, such as MOSFET's with raised source/drain extensions on a substrate with isolation trenches etched into the surface of the substrate. The inventive method provides thin first dielectric spacers on the side of a gate and gate oxide and extend from the top of the gate to the surface of the substrate. Raised source/drain extensions are placed on the surface of a substrate, which extend from the first dielectric spacers to the isolation trenches. Thicker second dielectric spacers are placed adjacent to the first dielectric spacers and extend from the top of the first dielectric spacers to the raised source/drain extensions. Raised source/drain regions are placed on the raised source/drain extensions, and extend from the isolation trenches to the second dielectric spacers. The inventive semiconductor devices provide for very shallow source drain extensions which results in a reduced short channel effect.

摘要翻译： 本发明的方法提供了改进的半导体器件，例如在衬底上具有升高的源极/漏极延伸的MOSFET，其中隔离沟槽蚀刻到衬底的表面中。 本发明的方法在栅极和栅极氧化物的一侧提供薄的第一介电间隔物，并且从栅极的顶部延伸到衬底的表面。 引出的源极/漏极延伸部被放置在从第一电介质间隔物延伸到隔离沟槽的衬底的表面上。 更厚的第二电介质间隔物被放置成与第一电介质间隔物相邻并且从第一介电间隔物的顶部延伸到升高的源极/漏极延伸部分。 升高的源极/漏极区域放置在凸起的源极/漏极延伸部上，并且从隔离沟槽延伸到第二电介质间隔物。 本发明的半导体器件提供非常浅的源极漏极延伸，这导致短沟道效应的降低。

公开(公告)号：US06800885B1

公开(公告)日：2004-10-05

申请号：US10385652

申请日：2003-03-12

申请人： Judy Xilin An ,  Bin Yu

发明人： Judy Xilin An ,  Bin Yu

IPC分类号： H01L2980

CPC分类号： H01L29/785 ,  H01L29/42392 ,  H01L29/66795 ,  H01L29/7856

摘要： An asymmetric double gate metal-oxide semiconductor field-effect transistor (MOSFET) includes a first fin formed on a substrate; a second fin formed on the substrate; a first gate formed adjacent first sides of the first and second fins, the first gate being doped with a first type of impurity; and a second gate formed between second sides of the first and second fins, the second gate being doped with a second type of impurity. An asymmetric all-around gate MOSFET includes multiple fins; a first gate structure doped with a first type of impurity and formed adjacent a first side of one of the fins; a second gate structure doped with the first type of impurity and formed adjacent a first side of another one of the fins; a third gate structure doped with a second type of impurity and formed between two of the fins; and a fourth gate structure formed at least partially beneath one or more of the fins.

摘要翻译： 非对称双栅极金属氧化物半导体场效应晶体管（MOSFET）包括在基板上形成的第一鳍片; 在所述基板上形成的第二翅片; 形成在所述第一和第二鳍片的第一侧附近的第一栅极，所述第一栅极掺杂有第一类型的杂质; 以及形成在所述第一和第二鳍片的第二侧之间的第二栅极，所述第二栅极掺杂有第二类型的杂质。 非对称全栅极MOSFET包括多个鳍片; 掺杂有第一类型杂质的第一栅极结构，并且邻近其中一个鳍片的第一侧形成; 掺杂有第一类型杂质的第二栅极结构，并且与另一个鳍片的第一侧相邻地形成; 掺杂有第二类杂质并形成在两个鳍之间的第三栅极结构; 以及至少部分地在一个或多个翅片下方形成的第四门结构。

公开(公告)号：US06706614B1

公开(公告)日：2004-03-16

申请号：US10145953

申请日：2002-05-15

申请人： Judy Xilin An ,  Bin Yu

发明人： Judy Xilin An ,  Bin Yu

IPC分类号： H01L2176

CPC分类号： H01L29/66742 ,  H01L29/78618 ,  H01L29/78684

摘要： A silicon-on-insulator(SOI) transistor. The SOI transistor having a source and a drain having a body disposed therebetween, the source being implanted with germanium to form an area of silicon-germanium adjacent a source/body junction in a lower portion of the source, the area of silicon-germanium in the source forming a hereto junction along a lower portion of the source/body junction.

摘要翻译： 绝缘体上硅（SOI）晶体管。 具有源极和漏极的SOI晶体管具有设置在其间的主体，源被注入锗以形成邻近源极的下部的源极/主体结的硅 - 锗的区域，硅 - 锗的面积 源沿着源/体结的下部形成本结。

公开(公告)号：US06448114B1

公开(公告)日：2002-09-10

申请号：US10128831

申请日：2002-04-23

申请人： Judy Xilin An ,  Bin Yu ,  William G. En

发明人： Judy Xilin An ,  Bin Yu ,  William G. En

IPC分类号： H01L218234

CPC分类号： H01L27/1203 ,  H01L21/84

摘要： A method of fabricating a silicon-on-insulator (SOI) chip having an active layer with a non-uniform thickness. The method includes the steps of providing a substrate; providing a buried oxide layer (BOX) on the substrate; providing an active layer on the BOX layer, the active layer having an initially uniform thickness; dividing the active layer into at least a first and a second tile; and altering the thickness of the active layer in the area of the second tile. The method also includes forming a plurality of partially depleted semiconductor devices from the active layer in the area of a thicker of the first and the second tiles and forming a plurality of fully depleted semiconductor devices from the active layer in the area of a thinner of the first and the second tiles.

摘要翻译： 一种制造具有不均匀厚度的有源层的绝缘体上硅（SOI）芯片的方法。 该方法包括提供基板的步骤; 在衬底上提供掩埋氧化物层（BOX）; 在BOX层上提供有源层，活性层具有最初均匀的厚度; 将活性层分成至少第一和第二瓦片; 并且改变第二瓦片区域中活性层的厚度。 该方法还包括在第一和第二瓦片较厚的区域中从有源层形成多个部分耗尽的半导体器件，并且在较薄的区域中从有源层形成多个完全耗尽的半导体器件 第一和第二个瓷砖。

公开(公告)号：US06414355B1

公开(公告)日：2002-07-02

申请号：US09770708

申请日：2001-01-26

申请人： Judy Xilin An ,  Bin Yu ,  William G. En

发明人： Judy Xilin An ,  Bin Yu ,  William G. En

IPC分类号： H01L2701

CPC分类号： H01L27/1203 ,  H01L21/84

摘要： A silicon-on-insulator (SOI) chip. The SOI chip has a substrate; a buried oxide (BOX) layer disposed on the substrate; and an active layer disposed on the BOX layer, the active layer divided into a first and a second tile, the first tile having a first thickness and the second tile having a second thickness, the second thickness being smaller than the first thickness. Also disclosed is a method of fabricating a silicon-on-insulator (SOI) chip having an active layer with a non-uniform thickness. The method includes the steps of providing a substrate; providing a buried oxide layer (BOX) on the substrate; providing an active layer on the BOX layer, the active layer having an initially uniform thickness; dividing the active layer into at least a first and a second tile; and altering the thickness of the active layer in the area of the second tile.

摘要翻译： 绝缘体上硅（SOI）芯片。 SOI芯片具有基板; 设置在基板上的掩埋氧化物（BOX）层; 以及设置在所述BOX层上的有源层，所述有源层被分为第一和第二瓦片，所述第一瓦片具有第一厚度，所述第二瓦片具有第二厚度，所述第二厚度小于所述第一厚度。 还公开了一种制造具有不均匀厚度的有源层的绝缘体上硅（SOI）芯片的方法。 该方法包括提供基板的步骤; 在衬底上提供掩埋氧化物层（BOX）; 在BOX层上提供有源层，活性层具有最初均匀的厚度; 将活性层分成至少第一和第二瓦片; 并且改变第二瓦片区域中活性层的厚度。

公开(公告)号：US07432557B1

公开(公告)日：2008-10-07

申请号：US10755344

申请日：2004-01-13

申请人： Matthew S. Buynoski ,  Judy Xilin An ,  Bin Yu

发明人： Matthew S. Buynoski ,  Judy Xilin An ,  Bin Yu

IPC分类号： H01L23/62

CPC分类号： H01L29/785 ,  H01L29/42384 ,  H01L29/66795 ,  H01L29/78603 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for forming one or more FinFET devices includes forming a source region and a drain region in an oxide layer, where the oxide layer is disposed on a substrate, and etching the oxide layer between the source region and the drain region to form a group of oxide walls and channels for a first device. The method further includes depositing a connector material over the oxide walls and channels for the first device, forming a gate mask for the first device, removing the connector material from the channels, depositing channel material in the channels for the first device, forming a gate dielectric for first device over the channels, depositing a gate material over the gate dielectric for the first device, and patterning and etching the gate material to form at least one gate electrode for the first device.

摘要翻译： 半导体器件包括源极区域，漏极区域和形成在源极区域和漏极区域之间的沟道组。 通道组中的至少一个通道通过氧化物结构与通道组中的另一个通道分离。 半导体器件还包括至少一个形成在该组沟道的至少一部分上的栅极。

公开(公告)号：US06872647B1

公开(公告)日：2005-03-29

申请号：US10429780

申请日：2003-05-06

申请人： Bin Yu ,  Judy Xilin An ,  Cyrus E. Tabery

发明人： Bin Yu ,  Judy Xilin An ,  Cyrus E. Tabery

IPC分类号： H01L21/033 ,  H01L21/336 ,  H01L29/06 ,  H01L29/786 ,  H01L21/3205 ,  H01L21/20 ,  H01L21/311

CPC分类号： H01L29/0665 ,  B82Y10/00 ,  H01L21/0337 ,  H01L29/0673 ,  H01L29/0676 ,  H01L29/66795 ,  H01L29/785

摘要： A method of forming multiple fins in a semiconductor device includes forming a structure having an upper surface and side surfaces on the semiconductor device. The semiconductor device includes a conductive layer located below the structure. The method also includes forming spacers adjacent the structure and selectively etching the spacers and the conductive layer to form the fins. The fins may be used in a FinFET device.

摘要翻译： 在半导体器件中形成多个散热片的方法包括形成具有半导体器件上表面和侧表面的结构。 半导体器件包括位于结构下方的导电层。 该方法还包括在该结构附近形成间隔物并选择性地蚀刻间隔物和导电层以形成翅片。 翅片可用于FinFET器件。