公开(公告)号：US20200176252A1

公开(公告)日：2020-06-04

申请号：US16689836

申请日：2019-11-20

Applicant: pSemi Corporation

Inventor： Robert Mark Englekirk ,  Keith Bargroff ,  Christopher C. Murphy ,  Tero Tapio Ranta ,  Simon Edward Willard

IPC: H01L21/02 ,  H01L21/8234 ,  H01L29/06 ,  H01L21/322 ,  H01L21/265 ,  H01L21/762 ,  H01L27/12 ,  H01L29/786

Abstract: Modified silicon-on-insulator (SOI) substrates having a trap rich layer, and methods for making such modifications. The modified regions eliminate or manage accumulated charge that would otherwise arise because of the interaction of the underlying trap rich layer and active layer devices undergoing transient changes of state, thereby eliminating or mitigating the effects of such accumulated charge on non-RF integrated circuitry fabricated on such substrates. Embodiments retain the beneficial characteristics of SOI substrates with a trap rich layer for RF circuitry requiring high linearity, such as RF switches, while avoiding the problems of a trap rich layer for circuitry that is sensitive to accumulated charge effects caused by the presence of the trap rich layer, such as non-RF analog circuitry and amplifiers (including power amplifiers and low noise amplifiers).

公开(公告)号：US10672726B2

公开(公告)日：2020-06-02

申请号：US15600579

申请日：2017-05-19

Applicant: pSemi Corporation

Inventor： Robert Mark Englekirk ,  Keith Bargroff ,  Christopher C. Murphy ,  Tero Tapio Ranta ,  Simon Edward Willard

IPC: H03B1/00 ,  H03K3/00 ,  H01L23/60 ,  H01L27/12 ,  H01L29/786 ,  H03K17/687 ,  H01L23/552 ,  H01L29/10 ,  H01L23/66 ,  H03K17/0412 ,  H01L21/762 ,  H03K17/0416 ,  H03K17/042 ,  H03K17/14

Abstract: Integrated circuits (ICs) that avoid or mitigate creation of changes in accumulated charge in a silicon-on-insulator (SOI) substrate, particularly an SOI substrate having a trap rich layer. In one embodiment, a FET is configured such that, in a standby mode, the FET is turned OFF while maintaining essentially the same VDS as during an active mode. In another embodiment, a FET is configured such that, in a standby mode, current flow through the FET is interrupted while maintaining essentially the same VGS as during the active mode. In another embodiment, a FET is configured such that, in a standby mode, the FET is switched into a very low current state (a “trickle current” state) that keeps both VGS and VDS close to their respective active mode operational voltages. Optionally, S-contacts may be formed in an IC substrate to create protected areas that encompass FETs that are sensitive to accumulated charge effects.

公开(公告)号：US20200076391A1

公开(公告)日：2020-03-05

申请号：US16676219

申请日：2019-11-06

Applicant: pSemi Corporation

Inventor： Tero Tapio Ranta ,  Keith Bargroff ,  Christopher C. Murphy ,  Robert Mark Englekirk

IPC: H03G3/30 ,  H03F1/30 ,  H03F1/56 ,  H03F3/19 ,  H03F3/21 ,  H03F3/24

Abstract: Temperature compensation circuits and methods for adjusting one or more circuit parameters of a power amplifier (PA) to maintain approximately constant Gain versus time during pulsed operation sufficient to substantially offset self-heating of the PA. Some embodiments compensate for PA Gain “droop” due to self-heating using a Sample and Hold (S&H) circuit. The S&H circuit samples and holds an initial temperature of the PA at commencement of a pulse. Thereafter, the S&H circuit generates a continuous measurement that corresponds to the temperature of the PA during the remainder of the pulse. A Gain Control signal is generated that is a function of the difference between the initial temperature and the operating temperature of the PA as the PA self-heats for the duration of the pulse. The Gain Control signal is applied to one or more adjustable or tunable circuits within a PA to offset the Gain droop of the PA.

公开(公告)号：US10276371B2

公开(公告)日：2019-04-30

申请号：US15600588

申请日：2017-05-19

Applicant: pSemi Corporation

Inventor： Robert Mark Englekirk ,  Keith Bargroff ,  Christopher C. Murphy ,  Tero Tapio Ranta ,  Simon Edward Willard

IPC: H01L29/06 ,  H01L21/02 ,  H01L21/8234 ,  H01L21/322 ,  H01L21/265 ,  H01L21/762 ,  H01L27/12

Abstract: Modified silicon-on-insulator (SOI) substrates having a trap rich layer, and methods for making such modifications. The modified regions eliminate or manage accumulated charge that would otherwise arise because of the interaction of the underlying trap rich layer and active layer devices undergoing transient changes of state, thereby eliminating or mitigating the effects of such accumulated charge on non-RF integrated circuitry fabricated on such substrates. Embodiments retain the beneficial characteristics of SOI substrates with a trap rich layer for RF circuitry requiring high linearity, such as RF switches, while avoiding the problems of a trap rich layer for circuitry that is sensitive to accumulated charge effects caused by the presence of the trap rich layer, such as non-RF analog circuitry and amplifiers (including power amplifiers and low noise amplifiers).

公开(公告)号：US20190057868A1

公开(公告)日：2019-02-21

申请号：US16167424

申请日：2018-10-22

Applicant: pSemi Corporation

Inventor： Robert Mark Englekirk ,  Keith Bargroff ,  Christopher C. Murphy ,  Tero Tapio Ranta ,  Simon Edward Willard

IPC: H01L21/02 ,  H01L21/322 ,  H01L29/06 ,  H01L21/265 ,  H01L21/762 ,  H01L21/8234

CPC classification number: H01L21/02658 ,  H01L21/265 ,  H01L21/3226 ,  H01L21/7624 ,  H01L21/823481 ,  H01L27/1203 ,  H01L27/1218 ,  H01L29/0649 ,  H01L29/78603

Abstract: Modified silicon-on-insulator (SOI) substrates having a trap rich layer, and methods for making such modifications. The modified regions eliminate or manage accumulated charge that would otherwise arise because of the interaction of the underlying trap rich layer and active layer devices undergoing transient changes of state, thereby eliminating or mitigating the effects of such accumulated charge on non-RF integrated circuitry fabricated on such substrates. Embodiments retain the beneficial characteristics of SOI substrates with a trap rich layer for RF circuitry requiring high linearity, such as RF switches, while avoiding the problems of a trap rich layer for circuitry that is sensitive to accumulated charge effects caused by the presence of the trap rich layer, such as non-RF analog circuitry and amplifiers (including power amplifiers and low noise amplifiers).

公开(公告)号：US20180262163A1

公开(公告)日：2018-09-13

申请号：US15908354

申请日：2018-02-28

Applicant: pSemi Corporation

Inventor： Ikumi Tokuda ,  Tero Tapio Ranta ,  Keith Bargroff ,  Christopher C. Murphy ,  Robert Mark Englekirk

IPC: H03F1/30 ,  H03F3/19 ,  H03F3/21

CPC classification number: H03F1/30 ,  G05F3/26 ,  H03F1/56 ,  H03F3/19 ,  H03F3/195 ,  H03F3/21 ,  H03F3/245 ,  H03F2200/129 ,  H03F2200/408 ,  H03F2200/411 ,  H03F2200/447 ,  H03F2200/451 ,  H03F2200/468 ,  H04B1/04 ,  H04B2001/0408

Abstract: Temperature compensation circuits and methods for adjusting one or more circuit parameters of a power amplifier (PA) to maintain approximately constant Gain versus time during pulsed operation sufficient to substantially offset self-heating of the PA. Some embodiments compensate for PA Gain “droop” due to self-heating using a Sample and Hold (S&H) circuit. Other embodiments include bias compensation circuits that directly regulate a bias signal to an amplifier stage as a function of localized heating of one or more of amplifier stages. Such bias compensation circuits include physical placement of at least one bias compensation circuit element in closer proximity to at least one amplifier stage than other bias compensation circuit elements. One bias compensation circuit embodiment includes a temperature-sensitive current mirror circuit for regulating the bias signal. Another bias compensation circuit embodiment includes a temperature-sensitive element having a positive temperature coefficient (PTC) for regulating the bias signal.

公开(公告)号：US12255587B2

公开(公告)日：2025-03-18

申请号：US18447207

申请日：2023-08-09

Applicant: pSemi Corporation

Inventor： Poojan Wagh ,  Kashish Pal ,  Robert Mark Englekirk ,  Tero Tapio Ranta ,  Keith Bargroff ,  Simon Edward Willard

IPC: H03F1/22 ,  H03F1/02 ,  H03F3/193

Abstract: Various methods and circuital arrangements for biasing one or more gates of stacked transistors of an amplifier are possible where the amplifier is configured to operate in at least an active mode and a standby mode. Circuital arrangements can reduce bias circuit and stacked transistors standby current during operation in the standby mode and to reduce impedance presented to the gates of the stacked transistors during operation in the active mode while maintaining voltage compliance of the stacked transistors during both modes of operation.

公开(公告)号：US12191833B2

公开(公告)日：2025-01-07

申请号：US17945652

申请日：2022-09-15

Applicant: pSemi Corporation

Inventor： Tero Tapio Ranta ,  Keith Bargroff ,  Christopher C. Murphy ,  Robert Mark Englekirk

IPC: H03F1/30 ,  H03F1/56 ,  H03F3/19 ,  H03F3/21 ,  H03F3/24 ,  H03G3/30

Abstract: Temperature compensation circuits and methods for adjusting one or more circuit parameters of a power amplifier (PA) to maintain approximately constant Gain versus time during pulsed operation sufficient to substantially offset self-heating of the PA. Some embodiments compensate for PA Gain “droop” due to self-heating using a Sample and Hold (S&H) circuit. The S&H circuit samples and holds an initial temperature of the PA at commencement of a pulse. Thereafter, the S&H circuit generates a continuous measurement that corresponds to the temperature of the PA during the remainder of the pulse. A Gain Control signal is generated that is a function of the difference between the initial temperature and the operating temperature of the PA as the PA self-heats for the duration of the pulse. The Gain Control signal is applied to one or more adjustable or tunable circuits within a PA to offset the Gain droop of the PA.

公开(公告)号：US12007803B2

公开(公告)日：2024-06-11

申请号：US18359513

申请日：2023-07-26

Applicant: pSemi Corporation

Inventor： Robert Mark Englekirk ,  Keith Bargroff ,  Christopher C. Murphy ,  Tero Tapio Ranta

IPC: G05F3/26 ,  G05F3/24 ,  H03M1/66 ,  H03M1/74

CPC classification number: G05F3/262 ,  G05F3/242 ,  H03M1/66 ,  H03M1/742

Abstract: A controllable temperature coefficient bias (CTCB) circuit is disclosed. The CTCB circuit can provide a bias to an amplifier. The CTCB circuit includes a variable with temperature (VWT) circuit having a reference circuit and a control circuit. The control circuit has a control output, a first current control element and a second current control element. Each current control element has a “controllable” resistance. One of the two current control elements may have a relatively high temperature coefficient and another a relatively low temperature coefficient. A controllable resistance of one of the current control elements increases when the controllable resistance of the other current control element decreases. However, the “total resistance” of the current control circuit remains constant with a constant temperature. The VWT circuit has an output with a temperature coefficient that is determined by the relative amount of current that flows through each current control element of the control circuit. A Current Digital to Analog Converter (IDAC) scales the output of the VWT and provides the scaled output to an amplifier bias input.

公开(公告)号：US11867584B2

公开(公告)日：2024-01-09

申请号：US17467251

申请日：2021-09-05

Applicant: pSemi Corporation

Inventor： Vishnu Srinivasan ,  Ion Opris ,  Keith Bargroff

IPC: G01L9/12 ,  G01L9/02 ,  H03M3/00 ,  B81B7/00

CPC classification number: G01L9/02 ,  B81B7/007 ,  B81B7/0058 ,  H03M3/414 ,  H03M3/458 ,  B81B2201/0264 ,  H03M3/438

Abstract: Methods and devices to mitigate time varying impairments in sensors are described. The application of such methods and devices to pressure sensors facing time varying parasitic capacitances due to water droplets is detailed. Benefits of auto-zeroing technique as adopted in disclosed devices is also described.