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公开(公告)号：US20160106355A1
公开(公告)日：2016-04-21
申请号：US14859263
申请日：2015-09-19
CPC分类号： A61B5/18 , A61B3/113 , A61B3/14 , A61B5/0075 , A61B5/1103 , B60K28/06 , B60W40/08 , B60W2040/0827 , G06K9/0061 , G06K9/4661
摘要： A system and a method for monitoring subject's eyes are disclosed. In one embodiment, spectral profiles of a frame substantially around a subject's eye are received from an image capturing device. Further, a state of the subject's eye in the frame is detected using the spectral profiles received from the image capturing device.
摘要翻译： 公开了一种用于监测受试者眼睛的系统和方法。 在一个实施例中，从图像捕获装置接收基本上围绕被检者眼睛的框架的光谱轮廓。 此外，使用从图像捕获装置接收的频谱分布来检测对象在帧中的眼睛的状态。
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公开(公告)号：US09239359B2
公开(公告)日：2016-01-19
申请号：US13626538
申请日：2012-09-25
申请人： IMEC , Stichting IMEC Nederland
IPC分类号： G01R31/3185 , G01R31/3177 , G01R31/317
CPC分类号： G01R31/318508 , G01R31/31717 , G01R31/3177 , G01R31/318511 , G01R31/318513 , G01R31/318572
摘要： A test access architecture is disclosed for 3D-SICs that allows for both pre-bond die testing and post-bond stack testing. The test access architecture is based on a modular test approach, in which the various dies, their embedded IP cores, the inter-die TSV-based interconnects, and the external I/Os can be tested as separate units to allow optimization of the 3D-SIC test flow. The architecture builds on and reuses existing design for test (DfT) hardware at the core, die, and product level. Test access is provided to an individual die stack via a test structure called a wrapper unit.
摘要翻译： 公开了用于3D-SIC的测试访问架构，其允许预键合芯片测试和后绑定堆叠测试。 测试访问架构基于模块化测试方法，其中各种模具，其嵌入式IP内核，基于芯片间TSV的互连和外部I / O可以作为单独的单元进行测试，从而优化3D -SIC测试流程。 该架构建立并重用现有的核心，管芯和产品级测试（DfT）硬件设计。 通过称为包装单元的测试结构将测试访问提供给单个管芯堆叠。
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公开(公告)号：US08658512B2
公开(公告)日：2014-02-25
申请号：US13382335
申请日：2010-07-01
申请人： Tom Sterken , Geert Altena , Martijn Goedbloed , Robert Puers
发明人： Tom Sterken , Geert Altena , Martijn Goedbloed , Robert Puers
IPC分类号： H01L21/20
摘要： A method for fabricating an out-of-plane variable overlap MEMS capacitor comprises: providing a substrate (40) comprising a first layer (41), a second layer (42), and a third layer (43) stacked on top of one another; and etching a plurality of first trenches (70) through the third layer (43), through the second layer (42), and into the first layer (41) using a single etching mask. Etching the plurality of first trenches (70) defines a plurality of first fingers (51) in the third layer (43) and a plurality of second fingers (52) in the first layer (41). By using a single mask, the process is self-aligned. The method further comprises removing the second layer (42) in a first region where the plurality of first trenches (70) are provided, thereby forming a spacing or gap between the plurality of first fingers (51) and the plurality of second fingers (52).
摘要翻译： 一种用于制造面外可变重叠MEMS电容器的方法包括：提供包括第一层（41），第二层（42）和堆叠在彼此顶部的第三层（43）的衬底（40） ; 以及通过所述第三层（43）通过所述第二层（42）蚀刻多个第一沟槽（70），并使用单个蚀刻掩模蚀刻到所述第一层（41）中。 蚀刻多个第一沟槽（70）在第三层（43）中限定多个第一指状物（51）和第一层（41）中的多个第二指状物（52）。 通过使用单个掩模，该过程是自对准的。 该方法还包括在设置有多个第一沟槽（70）的第一区域中移除第二层（42），从而在多个第一指状物（51）和多个第二指状物（52）之间形成间隔或间隙 ）。
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公开(公告)号：US20120171836A1
公开(公告)日：2012-07-05
申请号：US13382335
申请日：2010-07-01
申请人： Tom Sterken , Geert Altena , Martijn Goedbloed , Robert Puers
发明人： Tom Sterken , Geert Altena , Martijn Goedbloed , Robert Puers
IPC分类号： H01L21/02
摘要： A method for fabricating an out-of-plane variable overlap MEMS capacitor comprises: providing a substrate (40) comprising a first layer (41), a second layer (42), and a third layer (43) stacked on top of one another; and etching a plurality of first trenches (70) through the third layer (43), through the second layer (42), and into the first layer (41) using a single etching mask. Etching the plurality of first trenches (70) defines a plurality of first fingers (51) in the third layer (43) and a plurality of second fingers (52) in the first layer (41). By using a single mask, the process is self-aligned. The method further comprises removing the second layer (42) in a first region where the plurality of first trenches (70) are provided, thereby forming a spacing or gap between the plurality of first fingers (51) and the plurality of second fingers (52).
摘要翻译： 一种用于制造面外可变重叠MEMS电容器的方法包括：提供包括第一层（41），第二层（42）和堆叠在彼此顶部的第三层（43）的衬底（40） ; 以及通过所述第三层（43）通过所述第二层（42）蚀刻多个第一沟槽（70），并使用单个蚀刻掩模蚀刻到所述第一层（41）中。 蚀刻多个第一沟槽（70）在第三层（43）中限定多个第一指状物（51）和第一层（41）中的多个第二指状物（52）。 通过使用单个掩模，该过程是自对准的。 该方法还包括在设置有多个第一沟槽（70）的第一区域中移除第二层（42），从而在多个第一指状物（51）和多个第二指状物（52）之间形成间隔或间隙 ）。
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公开(公告)号：US11786125B2
公开(公告)日：2023-10-17
申请号：US17123101
申请日：2020-12-15
发明人： George Mikhail , Binh Vu , Jochen Walser , Dan Dlugos , Mark Fichman , Seulki Lee , Navid Shahriari , Erfan Sheikhi , Maria Op de Beeck
CPC分类号： A61B5/0031 , A61B5/1036 , A61B17/80 , A61B90/06 , A61B2090/064
摘要： An implantable device includes a substrate and protective cover that cooperate to define an enclosed sensor volume. A sealed enclosure is provided within the sensor volume, with an electronic component assembly (ECA) being located within the sealed enclosure. A flexible circuit board assembly (FCBA) is electrically coupled with the ECA through a wall of the sealed enclosure. At least one transducer is provided on the FCBA in contact with the substrate, and the FCBA is held apart from the enclosure via a polymeric spacer provided therebetween. An inert polymer fill is provided within the sensor volume external to the enclosure.
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公开(公告)号：US20220252450A1
公开(公告)日：2022-08-11
申请号：US17613529
申请日：2020-05-19
申请人： IMEC VZW , Stichting IMEC Nederland
摘要： A smart contact lens (400) for detecting a ratiometric change in an incident light (126) intensity is provided, including one or more, preferably concentric, rings (410-1, 410-2, . . . , 410-N) of a liquid crystal display, LCD, type, each ring being operable between a state having a lower attenuation of light and a state having a higher attenuation of light; a circuit (420, 100, 101) for detecting a ratiometric change in an incident light intensity; and a controller (430) configured to operate the one or more rings based on an intensity of an incident light and to, as a response to the circuit (420, 100, 10 101) detecting a ratiometric change in the intensity of the incident light from a higher intensity state to a lower intensity state indicating that at least a beginning of a blinking of an eye of a user has occurred, initiate a re-polarization of the one or more rings. A method of operating the smart contact lens and various uses of the circuit are also provided.
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公开(公告)号：US20220176136A1
公开(公告)日：2022-06-09
申请号：US17546616
申请日：2021-12-09
申请人： IMEC VZW , Stichting IMEC Nederland
发明人： Yao-Hong Liu , Barundeb Dutta
摘要： The present disclosure relates to a brain-computer interface system and method. In an example, a brain-computer interface system includes a data processing unit, a data transceiver unit, and a sensing or stimulation unit. The system also includes a first communication path between the data transceiver unit and the sensing or stimulation unit including a first downlink channel for transmitting power and data from the data transceiver unit to the data sensing unit and a first uplink channel for transmitting data from the sensing or stimulation unit to the data transceiver unit. The system may additionally include a second communication path between the data processing unit and the data transceiver unit including a second downlink channel for transmitting power and data from the data processing unit to the data transceiver unit and a second uplink channel for transmitting data from the data transceiver unit to the data processing unit.
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公开(公告)号：US20220077603A1
公开(公告)日：2022-03-10
申请号：US17466908
申请日：2021-09-03
申请人： IMEC VZW , Stichting IMEC Nederland
摘要： A circuit for optoelectronic down-conversion of a terahertz, THz, signal comprises a first photodiode and a second photodiode configured to be excited by an optical beat signal. The photodiodes are coupled in series through a common antenna. The terminals of the antenna are coupled to form an output terminal and the antenna is configured to receive the terahertz, THz, signal. The photodiodes thereby, via the optical beat signal, respectively, down-convert the THz signal and generate a current comprising an intermediate frequency, IF, component and a direct current, DC, component. The respective generated currents are summed at the output terminal, thereby obtaining the IF components and cancelling the DC components.
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公开(公告)号：US11223329B2
公开(公告)日：2022-01-11
申请号：US16788696
申请日：2020-02-12
发明人： Aritra Banerjee , Pierre Wambacq
摘要： A power amplifier circuitry (100) comprises: a transistor stack (110) comprising at least two stacked transistor units (112A, 112B, 112C) for amplifying input signals; wherein each stacked transistor unit (112A, 112B, 112C) comprises a plurality of controllable segments (120-1 to 120-N, 130-1 to 130-N, 140-1 to 140-N), each comprising a segment transistor (122, 132, 142), wherein source terminals (123, 133, 143) within each transistor unit are connected, drain terminals (125, 135, 145) within each transistor unit are connected and gate terminals (124, 134, 144) within each transistor unit are connected, wherein each segment transistor (122, 132, 142) further comprises a back gate terminal (126, 136, 146) for setting a body bias, wherein at least two of the segment transistors (122, 132, 142) within each transistor unit have independently connected back gate terminals (126, 136, 146); and a control unit (190) configured to control the body bias for selecting an amplifier class of each of the controllable segments (120-1 to 120-N, 130-1 to 130-N, 140-1 to 140-N) of each of the stacked transistor units (112A, 112B, 112C).
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公开(公告)号：US10200047B2
公开(公告)日：2019-02-05
申请号：US15605261
申请日：2017-05-25
发明人： Nereo Markulic , Yao-Hong Liu , Jan Craninckx
摘要： The disclosure provides a phase locked loop, PLL, for phase locking an output signal to a reference signal. The PLL comprises a reference path providing the reference signal to a first input of a phase detector, a feedback loop providing the output signal of the PLL as a feedback signal to a second input of the phase detector, a controllable oscillator generating the output signal based on at least a phase difference between reference and feedback signal, a digital-to-time converter, DTC, delaying a signal that is provided at one of the first and second input, a delay calculation path for calculating a DTC delay value. The PLL further comprises a randomization unit for generating and adding a random offset, i.e. a pseudo-random integer, to the delay value. The offset is such that a target output of the phase detector remains substantially unchanged.
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