公开(公告)号：US20070222483A1

公开(公告)日：2007-09-27

申请号：US11686739

申请日：2007-03-15

Applicant: Hae-Seung Lee

Inventor： Hae-Seung Lee

IPC: G11C27/02

CPC classification number: H03H19/004 ,  G11C7/06 ,  G11C27/026 ,  H03M1/0607 ,  H03M1/403 ,  H03M1/442 ,  H03M3/356

Abstract: A comparator based circuit with effective offset cancellation includes first and second amplifiers and an offset capacitor operatively connected to the first and second amplifiers. An offset voltage source generates an offset voltage. A first switch connects the offset voltage source to ground during a first time period. The first amplifier generates an output voltage in response to the first switch connecting the offset voltage source to ground during the first time period. A second switch connects the offset capacitor to ground during a second time period. The first switch disconnects the offset voltage source from ground during a third time period, and the second switch disconnects the offset capacitor from ground during the third time period.

Abstract translation: 具有有效偏移消除的基于比较器的电路包括第一和第二放大器以及可操作地连接到第一和第二放大器的偏移电容器。 偏移电压源产生偏移电压。 在第一时间段期间，第一开关将偏移电压源连接到地。 第一放大器响应于在第一时间段期间将偏移电压源连接到地的第一开关产生输出电压。 在第二时间段内，第二开关将偏移电容器接地。 第一个开关在第三个时间段内断开偏移电压源与地的连接，第二个开关在第三个时间段内将偏移电容器与地线断开。

公开(公告)号：US20070126619A1

公开(公告)日：2007-06-07

申请号：US11292624

申请日：2005-12-02

Applicant: Don McGrath

Inventor： Don McGrath

IPC: H03M1/12

CPC classification number: G01K7/01 ,  G01K2217/00 ,  H03M3/356 ,  H03M3/392 ,  H03M3/43 ,  H03M3/456

Abstract: A device and method for efficiently monitoring temperature and providing analog to digital conversion is described. In one embodiment, a single cell temperatures sensor and analog to digital converter, operable in two modes, is provided. The temperature sensor and analog to digital converter may share common components in order to further reduce the amount of substrate area required by the device.

Abstract translation: 描述了一种用于有效监测温度并提供模数转换的装置和方法。 在一个实施例中，提供了可在两种模式中操作的单电池温度传感器和模数转换器。 温度传感器和模数转换器可以共享共同的部件，以便进一步减少设备所需的基板面积。

公开(公告)号：US07091725B2

公开(公告)日：2006-08-15

申请号：US10810340

申请日：2004-03-26

Applicant: Pavel Horsky ,  Ivan Koudar

Inventor： Pavel Horsky ,  Ivan Koudar

IPC: G01R27/02 ,  G01R27/08

CPC classification number: G01D3/028 ,  H03M3/324 ,  H03M3/356

Abstract: A measurement method or system for measuring a physical value comprises, during a same clock cycle, forming an input signal, a reference signal and an offset signal, the input signal including a parasitic value and a useful measurement value. A relationship between the input signal where the parasitic value has been cancelled out, and the reference signal is derived. From this relationship, a value relating to the physical value is determined. The input signal, reference signal and offset signal are respectively associated with an input element, a reference element and a parasitic element. All elements have a common driving signal, and the parasitic value is depending on the common driving signal. The fact that different signals are formed during a same measurement cycle, and that these signals are sufficient to obtain the desired physical value, makes the measurement method or system of the present invention faster than prior art measurement methods or systems: only one conversion cycle is needed against two cycles needed for dual slope analog-to-digital conversion.

Abstract translation: 用于测量物理值的测量方法或系统包括在同一时钟周期内形成输入信号，参考信号和偏移信号，所述输入信号包括寄生值和有用测量值。 导出寄生值已被抵消的输入信号与参考信号之间的关系。 根据该关系，确定与物理值有关的值。 输入信号，参考信号和偏移信号分别与输入元件，参考元件和寄生元件相关联。 所有元件均具有公共驱动信号，寄生值取决于公共驱动信号。 在相同测量周期内形成不同信号，并且这些信号足以获得所需物理值的事实使得本发明的测量方法或系统比现有技术的测量方法或系统更快：只有一个转换周期是 需要双斜率模数转换所需的两个周期。

公开(公告)号：US07009541B1

公开(公告)日：2006-03-07

申请号：US10970213

申请日：2004-10-21

Applicant: Khiem Nguyen

Inventor： Khiem Nguyen

IPC: H03M3/00

CPC classification number: H03M3/356 ,  H03M3/454 ,  H03M3/464

Abstract: A novel circuit is used to monitor the common-mode voltage at the summing junctions of the first integrator in a continuous-time ΣΔ ADC, wherein the circuit produces a control voltage which adjusts the quiescent current of the feedback DAC to compensate for any common-mode offset current. Since the adjustment takes place within the feedback DAC, there is no extra noise added to the differential signal path. The implementation provides for no degradation to the SNR of the converter.

Abstract translation: 一个新颖的电路用于监视连续时间SigmaDelta ADC中第一个积分器的求和点处的共模电压，其中该电路产生一个控制电压，该电压调节反馈DAC的静态电流以补偿任何共模电压， 模式偏移电流。 由于调节发生在反馈DAC内，因此不会对差分信号路径加上额外的噪声。 该实施方案不会降低转换器的SNR。

公开(公告)号：US20050275575A1

公开(公告)日：2005-12-15

申请号：US11124436

申请日：2005-05-06

Applicant: Mario Motz

Inventor： Mario Motz

IPC: H03M3/00 ,  H03M3/02

CPC classification number: H03M3/356 ,  H03M3/34 ,  H03M3/43 ,  H03M3/454

Abstract: An integrator circuit has an integrator unit performed to generate an integrated signal from a modulated input signal. Additionally, the integrator circuit has an error feedback coupler connected to an output of the integrator unit and to an input of the integrator unit and formed to determine an error component from the integrated signal or from a signal derived from the integrated signal and to compensate the error component via the feedback in the modulated input signal.

Abstract translation: 积分器电路具有执行的积分器单元，以从调制的输入信号产生积分信号。 此外，积分器电路具有连接到积分器单元的输出和积分器单元的输入的误差反馈耦合器，并被形成为根据积分信号或从积分信号导出的信号来确定误差分量，并补偿 误差分量通过调制输入信号中的反馈。

公开(公告)号：US06501408B2

公开(公告)日：2002-12-31

申请号：US10156411

申请日：2002-05-28

Applicant: Willem Hendrik Groeneweg

Inventor： Willem Hendrik Groeneweg

IPC: H03M166

CPC classification number: H03M3/356 ,  H03M3/504

Abstract: A FIRDAC (20) is described, coupled to a noise-shaper (12) with a DC offset. The resulting offset of the FIRDAC itself is compensated by a compensation current source (Pcomp; Ncomp) which is continuously ON. The FIRDAC has a plurality of FIRDAC cells (40), each cell comprising at least one current source (50; 70). In a FIRDAC cell having a relatively small current source, a dummy transistor (80; 90) is formed in the free space. The compensation current source is formed as a parallel combination of certain dummy transistors. In a possible embodiment, each FIRDAC cell (40) comprises a stack comprising a D-flipflop (60), a PMOS current mirror (50) above the flipflop, and an NMOS current mirror (70) below the flipflop. In a cell with relatively small PMOS and NMOS current mirrors, a dummy current mirrors (80; 90) are formed in the substrate (100). A plurality of these dummy current mirrors (90; 80) are connected in parallel to constitute said compensation current source (Ncomp, Pcomp). FIG. 4.

Abstract translation: 描述了FIRDAC（20），其耦合到具有DC偏移的噪声整形器（12）。 FIRDAC本身产生的偏移由连续ON的补偿电流源（Pcomp; Ncomp）补偿。FIRDAC具有多个FIRDAC单元（40），每个单元包括至少一个电流源（50; 70）。 在具有相对小的电流源的FIRDAC电池中，在自由空间中形成虚拟晶体管（80; 90）。 补偿电流源形成为某些虚拟晶体管的并联组合。在可能的实施例中，每个FIRDAC单元（40）包括包括触发器（60），触发器上方的PMOS电流镜（50）的堆叠，以及 触发器下方的NMOS电流镜（70）。 在具有相对较小的PMOS和NMOS电流镜的电池中，在衬底（100）中形成虚拟电流镜（80; 90）。 多个虚拟电流镜（90; 80）并联连接，构成补偿电流源（Ncomp，Pcomp）。 图。 4。

公开(公告)号：US20010043152A1

公开(公告)日：2001-11-22

申请号：US09861703

申请日：2001-05-22

Inventor： Masahiro Kishida

IPC: H03M003/00

CPC classification number: H03F3/217 ,  H03F2200/331 ,  H03M3/356 ,  H03M3/43 ,  H03M3/438

Abstract: A digital switching amplifier in accordance with the present invention is provided with attenuation sections that attenuate respective 1-bit signals that have been subjected to the power amplification, and an offset voltage addition and adjustment section that adds adjustment voltages to output signals of the respective attenuation sections so that a D.C. voltage level difference between negative feedback signals which return to a delta sigma modulation circuit becomes substantially zero. This allows to ensurely provide a digital switching amplifier that can avoid that the gain with respect to positive and negative input signals change and easily avoid that the noise occurs in the lower frequency band due to an offset voltage.

Abstract translation: 根据本发明的数字开关放大器设置有衰减部分，其衰减已经经过功率放大的各个1位信号;以及偏移电压相加和调整部分，其将调节电压加到各个衰减的输出信号上 使得返回到ΔΣ调制电路的负反馈信号之间的直流电压电平差基本为零。 这允许确保提供数字开关放大器，其可以避免相对于正和负输入信号的增益改变并且容易避免由于偏移电压而在较低频带中发生噪声。

公开(公告)号：US12068760B2

公开(公告)日：2024-08-20

申请号：US17809488

申请日：2022-06-28

Applicant: Analog Devices International Unlimited Company

Inventor： Naiqian Ren ,  Roberto Sergio Matteo Maurino

IPC: H03M3/00

CPC classification number: H03M3/464 ,  H03M3/326 ,  H03M3/356 ,  H03M3/39 ,  H03M3/422 ,  H03M3/454

Abstract: Techniques to deliver a precision low noise reference voltage to a precision analog-to-digital converter without the need of a reference buffer or digital correction. In an example, a technique can use an integrated resistor divider and external capacitor to derive a low noise precision reference voltage either from the power supply of the ADC, or from an integrated reference source.

公开(公告)号：US20160380646A1

公开(公告)日：2016-12-29

申请号：US14751063

申请日：2015-06-25

Applicant: Intel IP Corporation

Inventor： John G. Kauffman ,  Krzysztof Dufrene

IPC: H03M3/00 ,  H03M1/46 ,  H03M1/06

CPC classification number: H03M3/356 ,  H03M1/00 ,  H03M1/0607 ,  H03M1/12 ,  H03M1/46 ,  H03M3/386 ,  H03M3/424 ,  H03M3/444 ,  H03M3/454 ,  H03M3/464

Abstract: Described is an apparatus which comprises: a first integrator to receive an input signal and to generate a first output; a second integrator to receive the first output or a version of the first output and to generate a second output; and an analog-to-digital converter (ADC) to quantize the second output into a digital representation, the ADC including a detection circuit to detect an overload condition in the second output.

Abstract translation: 描述了一种装置，其包括：第一积分器，用于接收输入信号并产生第一输出; 第二积分器，用于接收第一输出或第一输出的版本并产生第二输出; 以及将第二输出量化为数字表示的模数转换器（ADC），该ADC包括用于检测第二输出中的过载状况的检测电路。

公开(公告)号：US09503121B2

公开(公告)日：2016-11-22

申请号：US14516736

申请日：2014-10-17

Applicant: Infineon Technologies AG

Inventor： Elmar Bach ,  Patrizia Greco ,  Snezana Stojanovic ,  Dietmar Straeussnigg

IPC: H03M3/00

CPC classification number: H03M3/464 ,  H03M3/34 ,  H03M3/356 ,  H03M3/424 ,  H03M3/458

Abstract: A modulator is configured to respond to input swings by providing a feedback voltage via a feedback path to compromise an increase in noise and distortion power with increasing signal power at signal levels exceeding a predetermined threshold. A digital-to-analog converter (DAC) generates a feedback voltage with a resistor string biased with a given current and switches as a function of an input value to mitigate the voltage swing at a summing node.

Abstract translation: 调制器被配置为通过经由反馈路径提供反馈电压来响应于输入摆幅，以通过在超过预定阈值的信号电平上增加信号功率来危及噪声和失真功率的增加。 数模转换器（DAC）产生具有以给定电流偏置的电阻串的反馈电压，并根据输入值切换以减轻求和节点处的电压摆幅。