公开(公告)号：US20050285763A1

公开(公告)日：2005-12-29

申请号：US10936179

申请日：2004-09-08

Applicant: Khiem Nguyen ,  Robert Adams

Inventor： Khiem Nguyen ,  Robert Adams

IPC: H03H11/12 ,  H03M3/04 ,  H03M1/10

CPC classification number: H03M3/386 ,  H03J1/0091 ,  H03J2200/10 ,  H03M3/458

Abstract: A hybrid tuning circuit is used consisting of a digital finite state machine and an analog tuning circuit to effectively keep the RC product of the continuous time integrator constant across process, temperature, supply, and sampling rate variations. Since the implementation is continuous, the tracking is more accurate than traditional techniques. Using a carefully chosen clocking scheme, the technique gets rid of inter-symbol interference in the feedback DAC. The technique does not use a reference frequency, thereby eliminating the need for a user to identify a reference frequency.

Abstract translation: 使用混合调谐电路，包括数字有限状态机和模拟调谐电路，以有效地保持连续时间积分器的RC乘积在过程，温度，电源和采样率变化之间恒定。 由于实施是连续的，跟踪比传统技术更准确。 使用精心挑选的时钟方案，该技术消除了反馈DAC中的符号间干扰。 该技术不使用参考频率，从而消除了用户识别参考频率的需要。

公开(公告)号：US20050067103A1

公开(公告)日：2005-03-31

申请号：US10672420

申请日：2003-09-26

Applicant: Khiem Nguyen ,  Peter Satitpunwaycha ,  Alfred Mak

Inventor： Khiem Nguyen ,  Peter Satitpunwaycha ,  Alfred Mak

IPC: C23F1/00 ,  G03F1/08 ,  H01J37/32

CPC classification number: G03F1/80 ,  H01J37/321 ,  H01J37/32935

Abstract: A photomask etch chamber, which includes a substrate support member disposed inside the chamber. The substrate support member is configured to support a photomask substrate. The chamber further includes a ceiling disposed on the chamber and an endpoint detection system configured to detect a peripheral region of the photomask substrate.

Abstract translation: 光掩模蚀刻室，其包括设置在室内的基板支撑构件。 衬底支撑构件被配置为支撑光掩模衬底。 腔室还包括设置在腔室上的天花板和配置成检测光掩模衬底的周边区域的端点检测系统。

公开(公告)号：US20110129948A1

公开(公告)日：2011-06-02

申请号：US12592735

申请日：2009-12-02

Applicant: Robert L. Hsieh ,  Khiem Nguyen ,  Warren W. Flack ,  Andrew M. Hawryluk

Inventor： Robert L. Hsieh ,  Khiem Nguyen ,  Warren W. Flack ,  Andrew M. Hawryluk

IPC: H01L21/66 ,  G01B11/00

CPC classification number: G03F9/7084 ,  G03F9/7065 ,  G03F9/7076 ,  G03F9/708 ,  G03F9/7088 ,  H01L33/22

Abstract: A method of aligning a wafer when lithographically fabricating a light-emitting diode (LED). The method includes forming on the wafer at least one roughened alignment mark having a root-mean-square (RMS) surface roughness σS. The roughened alignment mark is formed as a consequence of forming a plasma etch to roughen a LED surface on which the wafer alignment mark resides. The method also includes imaging the at least one roughened wafer alignment mark with alignment light having a wavelength λA that is in the range from about 2 σS to about 8 σS. The method also includes comparing the detected image to an alignment reference to establish wafer alignment. Once wafer alignment is established, p-contacts and n-contacts can be formed on the LED upper surface in their proper locations.

Abstract translation: 在光刻制造发光二极管（LED）时对准晶片的方法。 该方法包括在晶片上形成至少一个具有均方根（RMS）表面粗糙度S的粗糙对准标记。 作为形成等离子体蚀刻以粗糙化晶片对准标记所在的LED表面的结果，形成粗糙化的对准标记。 该方法还包括用波长λA为约2至约8微米的对准光对至少一个粗糙化的晶片对准标记进行成像。 该方法还包括将检测到的图像与对准基准进行比较以建立晶片对准。 一旦晶圆对准建立，p型触点和n型触点就可以在它们正确位置的LED上表面上形成。

公开(公告)号：US20070159370A1

公开(公告)日：2007-07-12

申请号：US11616468

申请日：2006-12-27

Applicant: Paul Baginski ,  Robert Adams ,  Khiem Nguyen

Inventor： Paul Baginski ,  Robert Adams ,  Khiem Nguyen

IPC: H03M1/66

CPC classification number: H03M3/502 ,  H03H19/004

Abstract: A digital to analog converter (DAC) includes a first continuous-time stage that receives an input signal associated with a digital signal and performs continuous-time digital-to-analog conversion operations on the input signal. The first continuous-time stage outputs a first output signal. A second switched-capacitor stage receives the first output signal and performs switched-capacitor filtering of the first output signal. The second switched-capacitor stage outputs a second output signal that is sent to a low pass filter to form a continuous analog signal associated with the digital signal.

Abstract translation: 数模转换器（DAC）包括第一连续时段，其接收与数字信号相关联的输入信号，并对输入信号执行连续时间数模转换操作。 第一连续时段输出第一输出信号。 第二开关电容器级接收第一输出信号并执行第一输出信号的开关电容滤波。 第二开关电容器级输出发送到低通滤波器的第二输出信号以形成与数字信号相关联的连续模拟信号。

公开(公告)号：US07128806B2

公开(公告)日：2006-10-31

申请号：US10689783

申请日：2003-10-21

Applicant: Khiem Nguyen ,  Peter Satitpunwaycha ,  Alfred W. Mak

Inventor： Khiem Nguyen ,  Peter Satitpunwaycha ,  Alfred W. Mak

IPC: H01L21/306 ,  C23F1/00

CPC classification number: H01L21/68707 ,  H01J37/321 ,  H01J37/32623 ,  H01L21/68735

Abstract: Method and apparatus for supporting and transferring a substrate in a semiconductor wafer processing system are provided. In one aspect, an apparatus is provided for supporting a substrate comprising-a cover ring comprising a base having a bore disposed therethough, the base having an upper surface and one or more raised surfaces disposed adjacent the bore, wherein the raised surface comprise one or more first substrate support members disposed adjacent an edge of the bore and a capture ring disposed on the cover ring, the capture ring comprising a semi-circular annular ring having an inner perimeter corresponding to the bore of the cover ring and one or more second substrate support members disposed on the inner perimeter and adapted to receive a substrate, wherein the capture ring is adapted to mate with the cover ring and form one contiguous raised surface on the cover ring.

Abstract translation: 提供了用于在半导体晶片处理系统中支撑和转移衬底的方法和装置。 在一个方面，提供了一种用于支撑衬底的装置，包括：盖环，包括具有设置在其上的孔的基部，所述基部具有上表面和邻近所述孔设置的一个或多个凸起表面，其中所述凸起表面包括一个或 邻近孔的第一衬底支撑构件和设置在盖环上的捕获环，捕获环包括半圆环形环，其具有对应于盖环的孔的内周边和一个或多个第二衬底 支撑构件，其布置在内周边上并且适于接收基底，其中所述捕获环适于与所述盖环配合并在所述盖环上形成一个相邻的凸起表面。

公开(公告)号：US07095345B2

公开(公告)日：2006-08-22

申请号：US10936179

申请日：2004-09-08

Applicant: Khiem Nguyen ,  Robert W. Adams

Inventor： Khiem Nguyen ,  Robert W. Adams

IPC: H03M1/10

CPC classification number: H03M3/386 ,  H03J1/0091 ,  H03J2200/10 ,  H03M3/458

Abstract: A hybrid tuning circuit is used consisting of a digital finite state machine and an analog tuning circuit to effectively keep the RC product of the continuous time integrator constant across process, temperature, supply, and sampling rate variations. Since the implementation is continuous, the tracking is more accurate than traditional techniques. Using a carefully chosen clocking scheme, the technique gets rid of inter-symbol interference in the feedback DAC. The technique does not use a reference frequency, thereby eliminating the need for a user to identify a reference frequency.

Abstract translation: 使用混合调谐电路，包括数字有限状态机和模拟调谐电路，以有效地保持连续时间积分器的RC乘积在过程，温度，电源和采样率变化之间恒定。 由于实施是连续的，跟踪比传统技术更准确。 使用精心挑选的时钟方案，该技术消除了反馈DAC中的符号间干扰。 该技术不使用参考频率，从而消除了用户识别参考频率的需要。

公开(公告)号：US20060154388A1

公开(公告)日：2006-07-13

申请号：US11031400

申请日：2005-01-08

Applicant: Richard Lewington ,  Corey Collard ,  Scott Anderson ,  Khiem Nguyen

Inventor： Richard Lewington ,  Corey Collard ,  Scott Anderson ,  Khiem Nguyen

IPC: H01L21/66 ,  C23C14/00

CPC classification number: G03F1/30 ,  H01L21/31116 ,  H01L21/67742

Abstract: The embodiments of the invention relate to a method and apparatus for measuring the etch depth between etching for an alternate phase shift photomask in a semiconductor photomask processing system. The apparatus for measuring the etch depth of a substrate in an etch processing system comprises a measurement cell coupled to a mainframe of the etch processing system, and an etch depth measurement tool coupled to the bottom of the measurement cell, wherein an opening at the bottom of the measurement cell allows light beams to pass between the etch depth measurement tool and the substrate. The embodiments of the invention also relate to the method of preparing an alternate phase shift mask by partially etching the quartz substrate to an initial etch depth, followed by measuring the etch depth with an integrated measurement tool. The substrate is then etched and measured repeatedly until the targeted etch depth has been reached.

Abstract translation: 本发明的实施例涉及一种用于测量半导体光掩模处理系统中的替代相移光掩模的蚀刻之间的蚀刻深度的方法和装置。 用于在蚀刻处理系统中测量衬底的蚀刻深度的装置包括耦合到蚀刻处理系统的主机的测量单元和耦合到测量单元的底部的蚀刻深度测量工具，其中底部的开口 的测量单元允许光束在蚀刻深度测量工具和衬底之间通过。 本发明的实施例还涉及通过将石英衬底部分蚀刻到初始蚀刻深度，然后用集成测量工具测量蚀刻深度来制备交替相移掩模的方法。 然后重复蚀刻和测量衬底，直到达到目标蚀刻深度。

公开(公告)号：US08781213B2

公开(公告)日：2014-07-15

申请号：US13302308

申请日：2011-11-22

Applicant: Robert L. Hsieh ,  Khiem Nguyen ,  Warren W. Flack ,  Andrew M. Hawryluk

Inventor： Robert L. Hsieh ,  Khiem Nguyen ,  Warren W. Flack ,  Andrew M. Hawryluk

IPC: G06K9/00 ,  G03F9/00 ,  H01L33/22

CPC classification number: G03F9/7084 ,  G03F9/7065 ,  G03F9/7076 ,  G03F9/708 ,  G03F9/7088 ,  H01L33/22

Abstract: An alignment system for aligning a wafer when lithographically fabricating LEDs having an LED wavelength λLED is disclosed. The system includes the wafer. The wafer has a roughened alignment mark with a root-mean-square (RMS) surface roughness σS. The system has a lens configured to superimpose an image of the reticle alignment mark with an image of the roughened alignment mark. The roughened alignment marked image is formed with alignment light having a wavelength λA that is in the range from about 2σS to about 8σS. An image sensor detects the superimposed image. An image processing unit processes the detected superimposed image to measure an alignment offset between the wafer and the reticle.

Abstract translation: 公开了一种用于在光刻制造具有LED波长λLED的LED的晶片时对准晶片的对准系统。 该系统包括晶片。 晶片具有粗糙的对准标记，均方根（RMS）表面粗糙度S。 该系统具有配置为用掩模版对准标记的图像叠加掩模版对准标记的图像的透镜。 粗糙的对准标记图像由波长λA为约2＆Sgr; S至约8＆Sgr; S的对准光形成。 图像传感器检测叠加图像。 图像处理单元处理检测到的叠加图像以测量晶片和标线片之间的对准偏移。

公开(公告)号：US08088633B2

公开(公告)日：2012-01-03

申请号：US12592735

申请日：2009-12-02

Applicant: Robert L. Hsieh ,  Khiem Nguyen ,  Warren W. Flack ,  Andrew M. Hawryluk

Inventor： Robert L. Hsieh ,  Khiem Nguyen ,  Warren W. Flack ,  Andrew M. Hawryluk

IPC: G01R31/26 ,  H01L21/66 ,  H01L21/00 ,  G06K9/00 ,  H01L23/544 ,  B23K26/00 ,  B23K26/02 ,  B23K26/08 ,  F27D11/00

CPC classification number: G03F9/7084 ,  G03F9/7065 ,  G03F9/7076 ,  G03F9/708 ,  G03F9/7088 ,  H01L33/22

Abstract: A method of aligning a wafer when lithographically fabricating a light-emitting diode (LED). The method includes forming on the wafer at least one roughened alignment mark having a root-mean-square (RMS) surface roughness σS. The roughened alignment mark is formed as a consequence of forming a plasma etch to roughen a LED surface on which the wafer alignment mark resides. The method also includes imaging the at least one roughened wafer alignment mark with alignment light having a wavelength λA that is in the range from about 2σS to about 8σS. The method also includes comparing the detected image to an alignment reference to establish wafer alignment. Once wafer alignment is established, p-contacts and n-contacts can be formed on the LED upper surface in their proper locations.

Abstract translation: 在光刻制造发光二极管（LED）时对准晶片的方法。 该方法包括在晶片上形成至少一个具有均方根（RMS）表面粗糙度S的粗糙对准标记。 作为形成等离子体蚀刻以粗糙化晶片对准标记所在的LED表面的结果，形成粗糙化的对准标记。 该方法还包括用波长λA为约2至约8微米的对准光对至少一个粗糙化的晶片对准标记进行成像。 该方法还包括将检测到的图像与对准基准进行比较以建立晶片对准。 一旦晶圆对准建立，p型触点和n型触点就可以在它们正确位置的LED上表面上形成。

公开(公告)号：US07800447B2

公开(公告)日：2010-09-21

申请号：US12173703

申请日：2008-07-15

Applicant: Abhishek Bandyopadhyay ,  Khiem Nguyen

Inventor： Abhishek Bandyopadhyay ,  Khiem Nguyen

IPC: H03F3/26

CPC classification number: H03F3/45475 ,  H03F3/3022 ,  H03F3/45183 ,  H03F2200/135 ,  H03F2200/513 ,  H03F2203/30033 ,  H03F2203/45726

Abstract: A low-power, low-voltage feedback class AB operational amplifier is disclosed. The minimum supply voltage is one gate-source voltage and two saturation voltages. Currents on the output p-type and n-type transistors are monitored as part of the feedback loop control. Accurate monitoring is achieved by connecting current monitors directly to the corresponding voltage rail. Additional output stages may be selectively connected to the primary output stage to dynamically adjust to changes source conditions. Thus by connecting the appropriate number and type of additional output stages, continuous time adaptive power supply compensation is achieved. Both single ended and differential topologies are described.

Abstract translation: 公开了一种低功率，低电压反馈级AB运算放大器。 最小电源电压为一个栅源电压和两个饱和电压。 作为反馈回路控制的一部分，监视输出p型和n型晶体管上的电流。 通过将电流监视器直接连接到相应的电压轨来实现精确的监控。 另外的输出级可以选择性地连接到主输出级，以动态调整以改变源条件。 因此，通过连接适当数量和类型的附加输出级，实现连续时间自适应电源补偿。 描述了单端和差分拓扑。