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    Semiconductor memory cell
    31.
    发明授权
    Semiconductor memory cell 失效
    半导体存储单元

    公开(公告)号：US06229170B1

    公开(公告)日：2001-05-08

    申请号：US09280695

    申请日：1999-03-30

    申请人： Masato Sakao

    发明人： Masato Sakao

    IPC分类号： H01L27108

    CPC分类号： H01L27/10888 ,  H01L27/10814 ,  Y10S257/905 ,  Y10S257/907

    摘要： A pair of semiconductor memory cells comprises active regions having rectangular shapes, arranged in uniform intervals in plan view, said active regions constituting channel regions and source/drain regions of switching transistors; word lines arranged so as to be perpendicular to the active regions; and an extraction electrode connected to a bit line through bit a line contact formed in connection to the active regions constituting the pair of switching transistors.

    摘要翻译： 一对半导体存储单元包括在平面图中以均匀间隔布置的矩形形状的有源区域，所述有源区域构成开关晶体管的沟道区域和源极/漏极区域; 排列成垂直于有源区的字线; 以及连接到与构成所述一对开关晶体管的有源区域连接形成的线路接触的位线的引出电极。

    Integrated circuit memory devices having highly integrated SOI memory cells therein
    32.
    发明授权
    Integrated circuit memory devices having highly integrated SOI memory cells therein 有权
    在其中具有高度集成的SOI存储器单元的集成电路存储器件

    公开(公告)号：US06181014B2

    公开(公告)日：2001-01-30

    申请号：US09271519

    申请日：1999-03-18

    申请人： Kyu-Charn Park ,  Duck-Hyung Lee

    发明人： Kyu-Charn Park ,  Duck-Hyung Lee

    IPC分类号： H01L2348

    CPC分类号： H01L27/10858 ,  H01L27/10885 ,  H01L27/1203 ,  H01L2924/0002 ,  Y10S257/907 ,  Y10S257/908 ,  H01L2924/00

    摘要： Integrated circuit memory devices having highly integrated SOI memory cells therein include an SOI substrate having a semiconductor active layer therein. A first trench isolation region is also provided. The first trench isolation region extends into and partitions the semiconductor active layer into first and second active regions. These first and second active regions are preferably electrically isolated from each other by the first trench isolation region. First and second access transistors are provided in the first and second active regions, respectively, and a first electrically insulating layer is provided on the SOI substrate. A first bit line is also provided at a first level. The first bit line is electrically connected to a first source/drain region of the first access transistor by a first bit line contact. This first bit line contact extends through the first electrically insulating layer and contacts the first source/drain region of the first access transistor. A second electrically insulating layer is also provided on the first bit line, opposite said first electrically insulating layer and a second bit line is provided on the second electrically insulating layer at a second level above the first level. The second bit line is electrically connected to a first source/drain region of the second access transistor by a second bit line contact which extends through the first and second electrically insulating layers and contacts the first source/drain region of the second access transistor. Higher integration densities can be achieved by dividing the active layer into electrically isolated active regions and then forming bit lines at different levels which are electrically connected to access transistors within these isolated active regions.

    摘要翻译： 其中具有高度集成的SOI存储单元的集成电路存储器件包括其中具有半导体有源层的SOI衬底。 还提供了第一沟槽隔离区域。 第一沟槽隔离区延伸到半导体活性层并将其分隔成第一和第二有源区。 这些第一和第二有源区优选地通过第一沟槽隔离区彼此电隔离。 第一和第二存取晶体管分别设置在第一和第二有源区中，并且第一电绝缘层设置在SOI衬底上。 在第一级还提供第一位线。 第一位线通过第一位线接触电连接到第一存取晶体管的第一源极/漏极区域。 该第一位线接触件延伸穿过第一电绝缘层并接触第一存取晶体管的第一源极/漏极区域。 在第一位线上还设有第二电绝缘层，与第一电绝缘层相对，并且第二位线在第二电绝缘层上设置在高于第一电平的第二电平上。 第二位线通过延伸穿过第一和第二电绝缘层并接触第二存取晶体管的第一源/漏区的第二位线接触电连接到第二存取晶体管的第一源/漏区。 可以通过将有源层分为电隔离的有源区，然后形成与这些隔离的有源区内的存取晶体管电连接的不同电平的位线来实现更高的积分密度。

    Bi-level digit line architecture for high density DRAMs
    35.
    发明授权
    Bi-level digit line architecture for high density DRAMs 失效
    用于高密度DRAM的双电平数字线架构

    公开(公告)号：US5864181A

    公开(公告)日：1999-01-26

    申请号：US950471

    申请日：1997-10-15

    申请人： Brent Keeth

    发明人： Brent Keeth

    IPC分类号： H01L21/8242 ,  H01L23/522 ,  H01L27/108 ,  H01L23/48

    CPC分类号： H01L27/10885 ,  H01L23/5225 ,  H01L27/10897 ,  H01L2924/0002 ,  H01L2924/3011 ,  Y10S257/907 ,  Y10S257/908

    摘要： There is a bi-level bit line architecture. Specifically, there is a DRAM memory cell and cell array that allows for 6F**2 cell sizes and avoids the signal to noise problems. Uniquely, the digit lines are designed to lie on top of each other like a double decker overpass road. Additionally, this design allows each digit line to be routed on both conductor layers, for equal lengths of the array, to provide balanced impedance. Now noise will appear as a common mode noise on both lines, and not as differential mode noise that would degrade the sensing operation. Furthermore, digit to digit coupling is nearly eliminated because of the twist design.

    摘要翻译： 有一个双级位线架构。 具体来说，有一个DRAM存储单元和单元阵列允许6F ** 2单元大小，并避免了信噪比问题。 独特的是，数字线设计成彼此顶部，如双层天桥。 此外，该设计允许每个数字线路在两个导体层上布线，对于阵列的相同长度，以提供平衡阻抗。 现在噪声将作为两条线路上的共模噪声出现，而不是会降低感测操作的差模噪声。 此外，由于扭转设计，数字到数字耦合几乎消除了。

    Dynamic random access memory arrays and methods therefor
    36.
    发明授权
    Dynamic random access memory arrays and methods therefor 失效
    动态随机存取存储器阵列及其方法

    公开(公告)号：US5821592A

    公开(公告)日：1998-10-13

    申请号：US884853

    申请日：1997-06-30

    申请人： Heinz Hoenigschmid ,  John DeBrosse

    发明人： Heinz Hoenigschmid ,  John DeBrosse

    IPC分类号： H01L21/8242 ,  H01L27/108 ,  H01L29/68

    CPC分类号： H01L27/10805 ,  H01L27/10882 ,  Y10S257/905 ,  Y10S257/907

    摘要： A dynamic random access memory array having an array of memory cells. Individual cells of the array are addressable by a plurality of word lines and a plurality of bit lines. The memory cells are disposed in active areas of the array. The array of memory cells includes a first strip of memory cells. The dynamic random access memory array includes a lower metal layer and an upper metal layer disposed above the lower metal layer. The dynamic random access memory array further includes a dielectric layer disposed between the lower metal layer and the upper metal layer. There is further included a first bit line of the plurality of bit lines which includes a lower metal first bit line portion implemented in the lower metal layer. The lower metal first bit line portion is coupled to a first plurality of memory cells of the first strip of memory cells. The first bit line also includes an upper metal first bit line portion implemented in the upper metal layer. The upper metal first bit line portion is coupled to the lower first metal bit line portion by a first contact through the dielectric layer. The first contact is disposed above one of the active areas.

    摘要翻译： 一种具有存储器单元阵列的动态随机存取存储器阵列。 该阵列的单个单元可由多个字线和多个位线寻址。 存储单元被布置在阵列的有效区域中。 存储单元的阵列包括第一条存储单元。 动态随机存取存储器阵列包括下金属层和设置在下金属层上方的上金属层。 动态随机存取存储器阵列还包括设置在下金属层和上金属层之间的电介质层。 还包括多个位线的第一位线，其包括实现在下金属层中的下金属第一位线部分。 下金属第一位线部分耦合到第一条存储器单元的第一多个存储单元。 第一位线还包括实现在上金属层中的上金属第一位线部分。 上金属第一位线部分通过介电层的第一接触耦合到下部第一金属位线部分。 第一触点设置在有效区域之上。

    Fault-tolerant hierarchical bus system and method of operating same
    38.
    发明授权
    Fault-tolerant hierarchical bus system and method of operating same 失效
    容错分层总线系统及其操作方法

    公开(公告)号：US5666480A

    公开(公告)日：1997-09-09

    申请号：US484063

    申请日：1995-06-06

    申请人： Wingyu Leung ,  Fu-Chieh Hsu

    发明人： Wingyu Leung ,  Fu-Chieh Hsu

    IPC分类号： G06F12/16 ,  G06F11/00 ,  G06F11/10 ,  G06F11/20 ,  G06F12/06 ,  G06F13/00 ,  G06F13/40 ,  G11C29/00 ,  G11C29/04 ,  G11C29/48 ,  H01L21/66 ,  H01L27/02 ,  H04L5/14 ,  H04L25/02 ,  G06F11/34

    CPC分类号： H04L25/0272 ,  G06F11/10 ,  G06F11/1032 ,  G06F11/2007 ,  G06F12/0661 ,  G06F13/4077 ,  G11C29/006 ,  G11C29/08 ,  G11C29/48 ,  G11C29/76 ,  G11C29/808 ,  G11C29/832 ,  G11C29/88 ,  H01L22/22 ,  H04L25/026 ,  H04L5/1461 ,  G06F11/006 ,  G11C2029/0401 ,  G11C2029/0411 ,  G11C2029/4402 ,  G11C29/81 ,  G11C5/04 ,  H01L27/0203 ,  H04L25/028 ,  H04L25/029 ,  H04L25/0292 ,  Y10S257/907

    摘要： A fault-tolerant, high-speed wafer scale system comprises a plurality of functional modules, a parallel hierarchical bus which is fault-tolerant to defects in an interconnect network, and one or more bus masters. This bus includes a plurality of bus lines segmented into sections and linked together by programmable bus switches and bus transceivers or repeaters in an interconnect network. By: 1) use of small block size (512K bit) for the memory modules; 2) use of programmable identification register to facilitate dynamic address mapping and relatively easy incorporation of global redundancy; 3) Use of a grid structure for the bus to provide global redundancy for the interconnect network; 4) Use of a relatively narrow bus consisting of 13 signal lines to keep the total area occupied by the bus small; 5) Use of segmented bus lines connected by programmable switches and programmable bus transceivers to facilitate easy isolation of bus defects; 6) use of special circuit for bus transceivers and asynchronous handshakes to facilitate dynamic bus configuration; 7) use of programmable control register to facilitate run-time bus reconfiguration; 8) Use of spare bus lines to provide local redundancy for the bus; and 9) Use of spare rows and columns in the memory module to provide local redundancy, high defect tolerance in the hierarchical bus is obtained.

    摘要翻译： 容错的高速晶片秤系统包括多个功能模块，对互连网络中的缺陷容错的并行分层总线以及一个或多个总线主机。 该总线包括分段成多个总线线路，并通过互连网络中的可编程总线开关和总线收发器或中继器连接在一起。 通过：1）使用小块大小（512K位）作为内存模块; 2）使用可编程标识寄存器来促进动态地址映射并相对容易地整合全局冗余; 3）使用网格结构为总线提供互联网络的全局冗余; 4）使用由13条信号线组成的较窄的总线，使总线占用的总面积较小; 5）使用由可编程开关和可编程总线收发器连接的分段总线，以便于轻松隔离总线缺陷; 6）使用专用电路进行总线收发器和异步握手，方便动态总线配置; 7）使用可编程控制寄存器，方便运行时总线重新配置; 8）使用备用总线为总线提供局部冗余; 和9）在内存模块中使用备用行和列提供局部冗余，获得分层总线中的高缺陷容限。

    Semiconductor memory
    39.
    发明授权
    Semiconductor memory 失效
    半导体存储器

    公开(公告)号：US5332923A

    公开(公告)日：1994-07-26

    申请号：US925167

    申请日：1992-08-06

    申请人： Kiyoshi Takeuchi

    发明人： Kiyoshi Takeuchi

    IPC分类号： G11C11/401 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108 ,  H01L27/02 ,  H01L23/48 ,  H01L29/68

    CPC分类号： H01L27/10805 ,  Y10S257/907

    摘要： A semiconductor memory is provided which comprises memory cell regions disposed on a substrate, word lines which are connected respectively to the memory cells in the memory cell regions for controlling at least reading information from the memory cells, first bit lines which are formed in a first layer on the substrate and connected respectively to the memory cells for transmitting information, and second bit lines which are formed in a second layer and connected respectively to the memory cells for transmitting information, the second layer being formed on the substrate and electrically insulated from the first layer. The limitation of the layout upon the decrease of the bit line pitch can be eliminated, so that the reduction of the chip occupation area by shrinkage of areas between each adjacent memory cell regions can be realized. The first and second bit lines each is preferable to be patterned like stairs. The first and second bit lines are preferable to be disposed so as to go around the connecting area of the capacitor element for storing information and switching transistor in the memory cell.

    摘要翻译： 提供一种半导体存储器，其包括设置在基板上的存储单元区域，分别连接到存储单元区域中的存储单元的字线，用于至少控制来自存储单元的读取信息，第一位线形成在第一 层分别连接到用于发送信息的存储单元和分别形成在第二层中并分别连接到用于发送信息的存储单元的第二位线，第二层形成在基板上并与电绝缘 第一层 可以消除在位线节距减小时的布局限制，从而可以实现每个相邻的存储单元区域之间的区域的缩小来减少芯片占用面积。 优选地，第一和第二位线被图案化为楼梯。 第一位线和第二位线优选地布置成围绕存储单元中的信息和开关晶体管的电容器元件的连接区域。