公开(公告)号：US20210004334A1

公开(公告)日：2021-01-07

申请号：US16772765

申请日：2018-03-28

Applicant: INTEL CORPORATION

Inventor： Kun TIAN ,  Xiao ZHENG ,  Ashok RAJ ,  Sanjay KUMAR ,  Rajesh SANKARAN

IPC: G06F12/1036 ,  G06F9/455 ,  G06F12/1081

Abstract: Embodiment of this disclosure provides a mechanism to extend a workload instruction to include both untranslated and translated address space identifiers (ASIDs). In one embodiment, a processing device comprising a translation manager is provided. The translation manager receives a workload instruction from a guest application. The workload instruction comprises an untranslated (ASID) and a workload for an input/output (I/O) device. The untranslated ASID is translated to a translated ASID. The translated ASID inserted into a payload of the workload instruction. Thereupon, the payload is provided to a work queue of the I/O device to execute the workload based in part on at least one of: the translated ASID or the untranslated ASID.

公开(公告)号：US10884948B2

公开(公告)日：2021-01-05

申请号：US16414739

申请日：2019-05-16

Applicant: Advanced Micro Devices, Inc.

Inventor： Alexander D. Breslow

IPC: G06F12/1018 ,  G06F12/1036 ,  G06F12/1072 ,  G06F16/901

Abstract: A device includes an address translation table to, in each node of a set of nodes in the address translation table, store a key value and a hash function identifier, a hash engine coupled with the address translation table to, for each node in the set of nodes, calculate a hash result for the key value by executing a hash function identified by the hash function identifier, and a processing unit coupled with the hash engine to, in response to a request to translate a virtual memory address to a physical memory address, identify a physical memory region corresponding to the virtual memory address based on the calculated hash result for each node in the set of nodes.

公开(公告)号：US10831593B2

公开(公告)日：2020-11-10

申请号：US16238862

申请日：2019-01-03

Applicant: International Business Machines Corporation

Inventor： Lakshminarayana B. Arimilli ,  Richard L. Arndt ,  Bartholomew Blaner

IPC: G06F11/30 ,  G06F11/10 ,  G06F9/455 ,  G06F12/1036 ,  G06F13/40 ,  G06F13/16

Abstract: Hardware accelerator memory address translation fault resolution is provided. A hardware accelerator and a switchboard are in communication with a processing core. The hardware accelerator determines at least one memory address translation related to an operation having a fault. The operation and the fault memory address translation are flushed from the hardware accelerator including augmenting the operation with an entity identifier. The switchboard forwards the operation with the fault memory address translation and the entity identifier from the hardware accelerator to a second buffer. The operating system repairs the fault memory address translation. The operating system sends the operation to the processing core utilizing an effective address based on the entity identifier. The switchboard, supported by the processing core, forwards the operation with the repaired memory address translation to a first buffer and the hardware accelerator executes the operation with the repaired address.

公开(公告)号：US10747682B2

公开(公告)日：2020-08-18

申请号：US15912363

申请日：2018-03-05

Applicant: Intel Corporation

Inventor： Steven M. Bennett ,  Andrew V. Anderson ,  Gilbert Neiger ,  Richard Uhlig ,  Scott Dion Rodgers ,  Rajesh M. Sankaran ,  Camron Rust ,  Sebastian Schoenberg

IPC: G06F12/00 ,  G06F12/1027 ,  G06F12/1009 ,  G06F12/1036 ,  G06F9/30 ,  G06F12/02 ,  G06F9/455 ,  G06F12/0875 ,  G06F12/1045

Abstract: A processor including logic to execute an instruction to synchronize a mapping from a physical address of a guest of a virtualization based system (guest physical address) to a physical address of the host of the virtualization based system (host physical address), and stored in a translation lookaside buffer (TLB), with a corresponding mapping stored in an extended paging table (EPT) of the virtualization based system.

公开(公告)号：US10740249B2

公开(公告)日：2020-08-11

申请号：US16401889

申请日：2019-05-02

Applicant: Intel Corporation

Inventor： Jason W. Brandt ,  Sanjoy K. Mondal ,  Richard A. Uhlig ,  Gilbert Neiger ,  Robert T. George

IPC: G06F13/00 ,  G06F12/1036 ,  G06F9/48 ,  G06F12/1027 ,  G06F9/455 ,  G06F12/02 ,  G06F12/1045 ,  G06F12/12 ,  G06F12/0804 ,  G06F12/0891 ,  G06F12/109 ,  G06F12/123

Abstract: In one embodiment of the present invention, a method includes switching between a first address space and a second address space, determining if the second address space exists in a list of address spaces; and maintaining entries of the first address space in a translation buffer after the switching. In such manner, overhead associated with such a context switch may be reduced.

公开(公告)号：US10740126B2

公开(公告)日：2020-08-11

申请号：US16166010

申请日：2018-10-19

Applicant: Intel Corporation

Inventor： Mohammad Abdallah ,  Ankur Groen ,  Erika Gunadi ,  Mandeep Singh ,  Ravishankar Rao

IPC: G06F9/32 ,  G06F12/08 ,  G06F9/455 ,  G06F12/0875 ,  G06F12/1027 ,  G06F9/30 ,  G06F12/1036 ,  G06F9/38

Abstract: Methods for supporting wide and efficient front-end operation with guest architecture emulation are disclosed. As a part of a method for supporting wide and efficient front-end operation, upon receiving a request to fetch a first far taken branch instruction, a cache line that includes the first far taken branch instruction, a next cache line and a cache line located at the target of the first far taken branch instruction is read. Based on information that is accessed from a data table, the cache line and either the next cache line or the cache line located at the target is fetched in a single cycle.

公开(公告)号：US20200159670A1

公开(公告)日：2020-05-21

申请号：US16752754

申请日：2020-01-27

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Uwe BRANDT ,  Markus HELMS ,  Christian JACOBI ,  Markus KALTENBACH ,  Thomas KOEHLER ,  Frank LEHNERT

IPC: G06F12/1036 ,  G06F12/1009 ,  G06F9/455

Abstract: An address translation facility is provided for multiple virtualization levels, where a guest virtual address may be translated to a guest non-virtual address, the guest non-virtual address corresponding without translation to a host virtual address, and the host virtual address may be translated to a host non-virtual address, where translation within a virtualization level may be specified as a sequence of accesses to address translation tables. The address translation facility may include a first translation engine and a second translation engine, where the first and second translation engines each have capacity to perform address translation within a single virtualization level of the multiple virtualization levels. In operation, based on the first translation engine performing a guest level translation, the second translation engine may perform a host level translation of a resulting guest non-virtual address to a host non-virtual address based on the guest level translation by the first translation engine.

公开(公告)号：US20200026474A1

公开(公告)日：2020-01-23

申请号：US16528232

申请日：2019-07-31

Applicant: Cryptography Research, Inc.

Inventor： Ambuj Kumar ,  Roy Moss

IPC: G06F3/06 ,  G06F12/06 ,  G06F12/1036

Abstract: A virtual memory including virtual addresses may be generated. A first virtual address of the virtual memory may be mapped to a first physical address of a one-time programmable (OTP) memory of a device. Furthermore, a second virtual address of the virtual memory may be mapped to a second physical address of a static memory of the device. The virtual memory that is mapped to the OTP memory and the static memory may be provided for accessing of the data of the OTP memory of the device.

公开(公告)号：US10528721B2

公开(公告)日：2020-01-07

申请号：US15298416

申请日：2016-10-20

Applicant: INTEL CORPORATION

Inventor： Kapil Sood ,  Somnath Chakrabarti ,  Wei Shen ,  Carlos V. Rozas ,  Mona Vij ,  Vincent R. Scarlata

IPC: G06F21/53 ,  G06F9/4401 ,  G06F9/455 ,  G06F21/79 ,  G06F12/1036 ,  G06F12/109 ,  G06F12/14 ,  G06F21/57 ,  G06F8/61 ,  H04L12/24

Abstract: Methods and apparatus for implemented trusted packet processing for multi-domain separatization and security. Secure enclaves are created in system memory of a compute platform configured to support a virtualized execution environment including a plurality of virtual machines (VMs) or containers, each secure enclave occupying a respective protected portion of the system memory, wherein software code external from a secure enclave cannot access code or data within a secure enclave, and software code in a secure enclave can access code and data both within the secure enclave and external to the secure enclave. Software code for implementing packet processing operations is installed in the secure enclaves. The software in the secure enclaves is then executed to perform the packet processing operations. Various configurations of secure enclaves and software code may be implemented, including configurations supporting service chains both within a VM or contain or across multiple VMs or containers, as well a parallel packet processing operations.

公开(公告)号：US10528479B2

公开(公告)日：2020-01-07

申请号：US15612602

申请日：2017-06-02

Applicant: Kai-Ting Amy Wang ,  Peng Wu

Inventor： Kai-Ting Amy Wang ,  Peng Wu

IPC: G06F9/46 ,  G06F11/00 ,  G06F17/30 ,  G06F12/1027 ,  G06F12/1009 ,  G06F12/02 ,  G06F8/65 ,  G06F9/445 ,  G06F12/1036 ,  G06F9/4401 ,  G06F9/52 ,  G06F9/48

Abstract: System and method for managing migration of global variables on processing system during live program updates, including creating a shared data segment is created in a physical memory of the processing system, binding a logical address space of a first global variable data segment for a first version of a program to a physical address of the shared data segment, and binding a logical address space for a second global variable data segment for an update version of the program to the physical address of the shared data segment. The first global variable data segment and the second global variable data segment exist concurrently and each map to common global variables stored in the shared data segment.