公开(公告)号：US06765227B1

公开(公告)日：2004-07-20

申请号：US10116791

申请日：2002-04-04

Applicant: Bin Yu ,  William G. En ,  Judy Xilin An ,  Concetta E. Riccobene

Inventor： Bin Yu ,  William G. En ,  Judy Xilin An ,  Concetta E. Riccobene

IPC: H01L2906

CPC classification number: H01L29/66742 ,  H01L21/76256 ,  H01L29/1054 ,  H01L29/78687 ,  Y10S438/977

Abstract: A semiconductor-on-insulator (SOI) wafer. The wafer includes a silicon substrate, a buried oxide (BOX) layer disposed on the substrate, and an active layer disposed on the box layer. The active layer has an upper silicon layer disposed on a silicon-germanium layer. The silicon-germanium layer is disposed on a lower silicon layer. The silicon-germanium of the silicon-germanium layer is strained silicon-germanium and is about 200 Å to about 400 Å thick.

Abstract translation: 绝缘体上半导体（SOI）晶片。 晶片包括硅衬底，设置在衬底上的掩埋氧化物（BOX）层和设置在盒层上的有源层。 有源层具有设置在硅 - 锗层上的上硅层。 硅 - 锗层设置在下硅层上。 硅 - 锗层的硅 - 锗是应变的硅 - 锗，并且是大约至大约400埃。

公开(公告)号：US06762448B1

公开(公告)日：2004-07-13

申请号：US10405343

申请日：2003-04-03

Applicant: Ming-Ren Lin ,  Haihong Wang ,  Bin Yu

Inventor： Ming-Ren Lin ,  Haihong Wang ,  Bin Yu

IPC: H01L2708

CPC classification number: H01L29/785 ,  H01L21/823412 ,  H01L21/823437 ,  H01L27/088 ,  H01L29/66795 ,  H01L29/7842

Abstract: A semiconductor device includes a group of fin structures. The group of fin structures includes a conductive material and is formed by growing the conductive material in an opening of an oxide layer. The semiconductor device further includes a source region formed at one end of the group of fin structures, a drain region formed at an opposite end of the group of fin structures, and at least one gate.

Abstract translation: 半导体器件包括一组翅片结构。 翅片结构的组包括导电材料，并且通过在氧化物层的开口中生长导电材料而形成。 半导体器件还包括形成在鳍片结构组的一端处的源极区域，形成在鳍片结构组的相对端处的漏极区域和至少一个栅极。

公开(公告)号：US06756277B1

公开(公告)日：2004-06-29

申请号：US09779985

申请日：2001-02-09

Applicant: Bin Yu

Inventor： Bin Yu

IPC: H01L21336

CPC classification number: H01L29/66628 ,  H01L29/66545 ,  H01L29/7834

Abstract: A method of manufacturing an integrated circuit utilizes solid phase epitaxy to form an elevated source region and an elevated drain region. The method includes providing a mask structure including spacers, removing the mask structure, providing an amorphous semiconductor material and crystallizing the amorphous semiconductor material without damaging a high-k gate dielectric layer. The semiconductor material can be silicided. A shallow source/drain implant can also be provided.

Abstract translation: 集成电路的制造方法利用固相外延形成升高的源极区域和升高的漏极区域。 该方法包括提供包括间隔物的掩模结构，去除掩模结构，提供非晶半导体材料并使非晶半导体材料结晶而不损坏高k栅极电介质层。 半导体材料可以被硅化。 还可以提供浅源/漏植入物。

公开(公告)号：US06743687B1

公开(公告)日：2004-06-01

申请号：US10254882

申请日：2002-09-26

Applicant: Bin Yu

Inventor： Bin Yu

IPC: H01L21336

CPC classification number: H01L29/6653 ,  H01L21/26506 ,  H01L21/268 ,  H01L29/6659 ,  H01L29/7833

Abstract: Micro-miniaturized semiconductor devices having transistors with abrupt high concentration shallow source/drain extensions are fabricated by sequentially forming deep source/drain regions, pre-amorphizing intended shallow source/drain extension regions, ion implanting impurities into the pre-amorphized regions and then laser thermal annealing to crystallize the pre-amorphized regions and to activate the source/drain extensions. Embodiments include forming the deep source/drain regions using removable sidewall spacers on the gate electrode, removing the sidewall spacers, forming the ion implanted pre-amorphized source/drain exension implants, forming laser transparent oxide sidewall spacers on the gate electrode and laser thermal annealing through the oxide laser transparent sidewall spacers to selectively activate the source/drain extensions.

Abstract translation: 具有突变高浓度浅源极/漏极延伸的晶体管的微小型半导体器件通过依次形成深源极/漏极区域，将预先拟合的预期浅源极/漏极延伸区域，离子注入杂质进入预非晶化区域，然后激光器 热退火以使预非晶化区域结晶并激活源极/漏极延伸部分。 实施例包括使用栅电极上的可移除的侧壁间隔物形成深源极/漏极区域，去除侧壁间隔物，形成离子注入的预非晶化源极/漏极释放植入物，在栅电极上形成激光透明氧化物侧壁间隔物和激光热退火 通过氧化物激光器透明侧壁间隔件来选择性地激活源极/漏极延伸部分。

公开(公告)号：US06743680B1

公开(公告)日：2004-06-01

申请号：US09599141

申请日：2000-06-22

Applicant: Bin Yu

Inventor： Bin Yu

IPC: H01L21336

CPC classification number: H01L29/0847 ,  H01L21/26506 ,  H01L21/268 ,  H01L21/28194 ,  H01L21/28202 ,  H01L21/28211 ,  H01L29/1054 ,  H01L29/51 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66477 ,  H01L29/665 ,  H01L29/7833 ,  H01L29/7842 ,  Y10S438/933

Abstract: A method of manufacturing an integrated circuit includes providing an amorphous semiconductor material including germanium, annealing the amorphous semiconductor material, and doping to form a source location and a drain location. The semiconductor material containing germanium can increase the charge mobility associated with the transistor.

Abstract translation: 制造集成电路的方法包括提供包括锗的非晶半导体材料，退火非晶半导体材料和掺杂以形成源极位置和漏极位置。 含锗的半导体材料可以增加与晶体管相关的电荷迁移率。

公开(公告)号：US06716686B1

公开(公告)日：2004-04-06

申请号：US10613997

申请日：2003-07-08

Applicant: Matthew S. Buynoski ,  Judy Xilin An ,  Bin Yu

Inventor： Matthew S. Buynoski ,  Judy Xilin An ,  Bin Yu

IPC: H01L2100

CPC classification number: H01L29/785 ,  H01L29/42384 ,  H01L29/66795 ,  H01L29/78603 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method for forming one or more FinFET devices includes forming a source region and a drain region in an oxide layer, where the oxide layer is disposed on a substrate, and etching the oxide layer between the source region and the drain region to form a group of oxide walls and channels for a first device. The method further includes depositing a connector material over the oxide walls and channels for the first device, forming a gate mask for the first device, removing the connector material from the channels, depositing channel material in the channels for the first device, forming a gate dielectric for first device over the channels, depositing a gate material over the gate dielectric for the first device, and patterning and etching the gate material to form at least one gate electrode for the first device.

Abstract translation: 用于形成一个或多个FinFET器件的方法包括在氧化物层中形成源极区域和漏极区域，其中氧化物层设置在衬底上，并且蚀刻源极区域和漏极区域之间的氧化物层以形成基团 的第一装置的氧化物壁和通道。 该方法还包括在第一器件的氧化物壁和通道上沉积连接器材料，形成用于第一器件的栅极掩模，从通道移除连接器材料，将沟道材料沉积在第一器件的通道中，形成栅极 在沟道上的第一器件的电介质，在第一器件的栅极电介质上沉积栅极材料，以及图案化和蚀刻栅极材料以形成用于第一器件的至少一个栅电极。

公开(公告)号：US06689671B1

公开(公告)日：2004-02-10

申请号：US10151946

申请日：2002-05-22

Applicant: Bin Yu ,  Derick J. Wristers

Inventor： Bin Yu ,  Derick J. Wristers

IPC: H01L2120

CPC classification number: H01L29/6659 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/0251 ,  H01L21/02532 ,  H01L21/02667 ,  H01L21/26506 ,  H01L21/26513 ,  H01L29/78687

Abstract: A method of manufacturing a semiconductor device, comprising steps of: (a) providing a semiconductor substrate comprising a strained lattice semiconductor layer at an upper surface thereof and having a pre-selected amount of lattice strain; (b) forming a device structure in the semiconductor substrate by a process comprising forming at least one amorphous region in at least one portion of the strained lattice semiconductor layer; and (c) thermal annealing at a minimum temperature sufficient to effect epitaxial re-crystallization of the at least one amorphous region to re-form a strained lattice semiconductor layer having substantially the pre-selected amount of lattice strain, whereby strain relaxation of the strained lattice semiconductor arising from thermal annealing is substantially eliminated or minimized.

Abstract translation: 一种制造半导体器件的方法，包括以下步骤：（a）在其上表面提供包括应变晶格半导体层并具有预选量的晶格应变的半导体衬底;（b）在 半导体衬底，其包括在应变晶格半导体层的至少一部分中形成至少一个非晶区; 和（c）在足以实现所述至少一个非晶区域的外延再结晶的最小温度下的热退火以重新形成具有基本上预选量的晶格应变的应变晶格半导体层，由此应变松弛 基本消除或最小化由热退火产生的晶格半导体。

公开(公告)号：US06680233B2

公开(公告)日：2004-01-20

申请号：US09974167

申请日：2001-10-09

Applicant: Bin Yu ,  Qi Xiang ,  HaiHong Wang

Inventor： Bin Yu ,  Qi Xiang ,  HaiHong Wang

IPC: H01L21336

CPC classification number: H01L29/4983 ,  H01L29/6653 ,  H01L29/6659

Abstract: A semiconductor device and method of manufacture. A liner composed of a high-K material having a relative permittivity of greater than 10 is formed adjacent at least the sidewalls of a gate. Sidewall spacers are formed adjacent the gate and spaced apart from the gate by the liner. The liner can be removed using an etch process that has substantially no reaction with a gate dielectric of the gate.

Abstract translation: 半导体器件及其制造方法。 由栅极的至少侧壁形成由相对介电常数大于10的高K材料构成的衬垫。 侧壁间隔件形成在门附近并且通过衬套与门隔开。 可以使用与栅极的栅极电介质基本上没有反应的蚀刻工艺来去除衬里。

公开(公告)号：US06656749B1

公开(公告)日：2003-12-02

申请号：US10013354

申请日：2001-12-13

Applicant: Eric N. Paton ,  Robert B. Ogle ,  Bin Yu ,  Cyrus E. Tabery ,  Qi Xiang

Inventor： Eric N. Paton ,  Robert B. Ogle ,  Bin Yu ,  Cyrus E. Tabery ,  Qi Xiang

IPC: H01L2100

CPC classification number: H01L21/02675 ,  H01L21/2026 ,  H01L21/268 ,  H01L22/12 ,  H01L22/20 ,  H01L29/6659

Abstract: A method of manufacturing a semiconductor device includes thermal annealing source/drain regions with a laser, measuring a depth of the source/drain regions, and adjusting a parameter of the laser used in the thermal annealing process. After the laser is adjusted, the source/drain regions are laser thermal annealed again until a desired depth of the source/drain regions is obtained. An apparatus for processing a semiconductor device includes a chamber, a laser, a measuring device, and a controller. The semiconductor device is positioned within the chamber for processing. The laser is used to laser thermal anneal the semiconductor device within the chamber. The measuring device measures a depth of source/drain regions in the semiconductor device when the semiconductor device is within the chamber, and the controller receives measurement information from the measuring device and adjusts parameters of the laser.

Abstract translation: 制造半导体器件的方法包括：用激光热退火源极/漏极区域，测量源极/漏极区域的深度，以及调整在热退火过程中使用的激光器的参数。 在调整激光器之后，源极/漏极区域被再次激光热退火，直到得到所需的源极/漏极区域的深度。 一种用于处理半导体器件的装置，包括腔室，激光器，测量装置和控制器。 半导体器件位于腔室内用于处理。 激光器用于对腔室内的半导体器件进行激光热退火。 当半导体器件在腔室内时，测量装置测量半导体器件中的源极/漏极区域的深度，并且控制器从测量装置接收测量信息并调整激光器的参数。

公开(公告)号：US06566213B2

公开(公告)日：2003-05-20

申请号：US09824123

申请日：2001-04-02

Applicant: William G. En ,  Srinath Krishnan ,  Dong-Hyuk Ju ,  Bin Yu

Inventor： William G. En ,  Srinath Krishnan ,  Dong-Hyuk Ju ,  Bin Yu

IPC: H01L21336

CPC classification number: H01L29/66507 ,  H01L21/28518 ,  H01L21/823443 ,  H01L29/41733 ,  H01L29/458 ,  H01L29/6653 ,  H01L29/66772 ,  H01L29/78621

Abstract: A transistor device formed on a semiconductor-on-insulator (SOI) substrate with a buried oxide (BOX) layer disposed thereon and an active layer disposed on the BOX layer having active regions defined by isolation trenches. The device includes a gate defining a channel interposed between a source and a drain formed within the active region of the SOI substrate. Further, the device includes a plurality of thin silicide layers formed on the source and the drain. Additionally, at least an upper silicide layer of the plurality of thin silicide layers extends beyond a lower silicide layer. Further still, the device includes a disposable spacer used in the formation of the device. The device further includes a second plurality of thin silicide layers formed on a polysilicon electrode of the gate.

Abstract translation: 一种在绝缘体上半导体（SOI）衬底上形成的埋置氧化物（BOX）层的晶体管器件，以及设置在具有由隔离沟槽限定的有源区域的BOX层上的有源层。 该器件包括限定插入在SOI衬底的有源区域内形成的源极和漏极之间的沟道的栅极。 此外，该器件包括形成在源极和漏极上的多个薄硅化物层。 另外，多个薄硅化物层中的至少一个上硅化物层延伸超过下硅化物层。 此外，该装置还包括用于形成装置的一次性间隔件。 该器件还包括形成在栅极的多晶硅电极上的第二多个薄硅化物层。