公开(公告)号：US06787854B1

公开(公告)日：2004-09-07

申请号：US10385753

申请日：2003-03-12

Applicant: Chih-Yuh Yang ,  Shibly S. Ahmed ,  Srikanteswara Dakshina-Murthy ,  Cyrus E. Tabery ,  Haihong Wang ,  Bin Yu

Inventor： Chih-Yuh Yang ,  Shibly S. Ahmed ,  Srikanteswara Dakshina-Murthy ,  Cyrus E. Tabery ,  Haihong Wang ,  Bin Yu

IPC: H01L218238

CPC classification number: H01L29/7853 ,  H01L29/66818

Abstract: A method for forming a fin structure on a silicon-on-insulator (SOI) wafer that includes a silicon layer on an insulating layer that is formed over a semiconductor substrate includes etching the silicon layer using a first etch procedure, etching, following the first etch procedure, the silicon layer using a second etch procedure, and etching, following the second etch procedure, the silicon layer using a third etch procedure to form a T-shaped fin structure.

Abstract translation: 一种在绝缘体上硅（SOI）晶片上形成翅片结构的方法，包括在半导体衬底上形成的绝缘层上的硅层，包括使用第一蚀刻步骤蚀刻硅层，然后蚀刻第一 蚀刻步骤，使用第二蚀刻步骤的硅层，以及在第二蚀刻程序之后，使用第三蚀刻工艺蚀刻硅层以形成T形翅片结构。

公开(公告)号：US06787424B1

公开(公告)日：2004-09-07

申请号：US09780043

申请日：2001-02-09

Applicant: Bin Yu

Inventor： Bin Yu

IPC: H01L21336

CPC classification number: H01L29/66772 ,  H01L29/41733 ,  H01L29/78618 ,  H01L29/78684

Abstract: A method of manufacturing an integrated circuit utilizes a thin film substrate. The method includes providing a mask structure on a top surface of the thin film, depositing a semiconductor material above the top surface of the thin film and the mask structure, removing the semiconductor material to a level below the top surface of the mask structure, siliciding the semiconductor material, and providing a gate structure in an aperture formed by removing the mask structure. The transistor can be a fully depleted transistor having material for siliciding source and drain regions.

Abstract translation: 集成电路的制造方法利用薄膜基板。 该方法包括在薄膜的顶表面上提供掩模结构，在半导体材料的上表面和掩模结构之上沉积半导体材料，将半导体材料去除到掩模结构的顶表面以下的水平，硅化 半导体材料，并且通过去除掩模结构形成的孔中提供栅极结构。 晶体管可以是具有用于硅化源极和漏极区域的材料的完全耗尽的晶体管。

公开(公告)号：US06780789B1

公开(公告)日：2004-08-24

申请号：US10230198

申请日：2002-08-29

Applicant: Bin Yu ,  Robert B. Ogle ,  Eric N. Paton ,  Cyrus E. Tabery ,  Qi Xiang

Inventor： Bin Yu ,  Robert B. Ogle ,  Eric N. Paton ,  Cyrus E. Tabery ,  Qi Xiang

IPC: H01L2131

CPC classification number: H01L21/28185 ,  H01L21/02238 ,  H01L21/02255 ,  H01L21/268 ,  H01L21/31662 ,  H01L29/665 ,  H01L29/6659

Abstract: Ultra-thin gate oxides are formed by exposing the upper surface of a substrate to a pulsed laser light beam in an atmosphere containing oxygen. Embodiments include exposing a silicon substrate to a pulsed laser light beam at a radiant fluence of 0.1 to 0.8 joules/cm2 for 1 to 10 nanoseconds to form a gate oxide layer having a thickness of 3 Å to 8 Å, e.g., 3 Å to 5 Å.

Abstract translation: 通过在包含氧的气​​氛中将衬底的上表面暴露于脉冲激光束来形成超薄栅极氧化物。 实施例包括将硅衬底以0.1至0.8焦耳/平方厘米的辐射通量暴露于脉冲激光束1至10纳秒以形成厚度为3至8的栅极氧化物层，例如3 Å至5Å。

公开(公告)号：US06765227B1

公开(公告)日：2004-07-20

申请号：US10116791

申请日：2002-04-04

Applicant: Bin Yu ,  William G. En ,  Judy Xilin An ,  Concetta E. Riccobene

Inventor： Bin Yu ,  William G. En ,  Judy Xilin An ,  Concetta E. Riccobene

IPC: H01L2906

CPC classification number: H01L29/66742 ,  H01L21/76256 ,  H01L29/1054 ,  H01L29/78687 ,  Y10S438/977

Abstract: A semiconductor-on-insulator (SOI) wafer. The wafer includes a silicon substrate, a buried oxide (BOX) layer disposed on the substrate, and an active layer disposed on the box layer. The active layer has an upper silicon layer disposed on a silicon-germanium layer. The silicon-germanium layer is disposed on a lower silicon layer. The silicon-germanium of the silicon-germanium layer is strained silicon-germanium and is about 200 Å to about 400 Å thick.

Abstract translation: 绝缘体上半导体（SOI）晶片。 晶片包括硅衬底，设置在衬底上的掩埋氧化物（BOX）层和设置在盒层上的有源层。 有源层具有设置在硅 - 锗层上的上硅层。 硅 - 锗层设置在下硅层上。 硅 - 锗层的硅 - 锗是应变的硅 - 锗，并且是大约至大约400埃。

公开(公告)号：US06756277B1

公开(公告)日：2004-06-29

申请号：US09779985

申请日：2001-02-09

Applicant: Bin Yu

Inventor： Bin Yu

IPC: H01L21336

CPC classification number: H01L29/66628 ,  H01L29/66545 ,  H01L29/7834

Abstract: A method of manufacturing an integrated circuit utilizes solid phase epitaxy to form an elevated source region and an elevated drain region. The method includes providing a mask structure including spacers, removing the mask structure, providing an amorphous semiconductor material and crystallizing the amorphous semiconductor material without damaging a high-k gate dielectric layer. The semiconductor material can be silicided. A shallow source/drain implant can also be provided.

Abstract translation: 集成电路的制造方法利用固相外延形成升高的源极区域和升高的漏极区域。 该方法包括提供包括间隔物的掩模结构，去除掩模结构，提供非晶半导体材料并使非晶半导体材料结晶而不损坏高k栅极电介质层。 半导体材料可以被硅化。 还可以提供浅源/漏植入物。

公开(公告)号：US06743687B1

公开(公告)日：2004-06-01

申请号：US10254882

申请日：2002-09-26

Applicant: Bin Yu

Inventor： Bin Yu

IPC: H01L21336

CPC classification number: H01L29/6653 ,  H01L21/26506 ,  H01L21/268 ,  H01L29/6659 ,  H01L29/7833

Abstract: Micro-miniaturized semiconductor devices having transistors with abrupt high concentration shallow source/drain extensions are fabricated by sequentially forming deep source/drain regions, pre-amorphizing intended shallow source/drain extension regions, ion implanting impurities into the pre-amorphized regions and then laser thermal annealing to crystallize the pre-amorphized regions and to activate the source/drain extensions. Embodiments include forming the deep source/drain regions using removable sidewall spacers on the gate electrode, removing the sidewall spacers, forming the ion implanted pre-amorphized source/drain exension implants, forming laser transparent oxide sidewall spacers on the gate electrode and laser thermal annealing through the oxide laser transparent sidewall spacers to selectively activate the source/drain extensions.

Abstract translation: 具有突变高浓度浅源极/漏极延伸的晶体管的微小型半导体器件通过依次形成深源极/漏极区域，将预先拟合的预期浅源极/漏极延伸区域，离子注入杂质进入预非晶化区域，然后激光器 热退火以使预非晶化区域结晶并激活源极/漏极延伸部分。 实施例包括使用栅电极上的可移除的侧壁间隔物形成深源极/漏极区域，去除侧壁间隔物，形成离子注入的预非晶化源极/漏极释放植入物，在栅电极上形成激光透明氧化物侧壁间隔物和激光热退火 通过氧化物激光器透明侧壁间隔件来选择性地激活源极/漏极延伸部分。

公开(公告)号：US06743680B1

公开(公告)日：2004-06-01

申请号：US09599141

申请日：2000-06-22

Applicant: Bin Yu

Inventor： Bin Yu

IPC: H01L21336

CPC classification number: H01L29/0847 ,  H01L21/26506 ,  H01L21/268 ,  H01L21/28194 ,  H01L21/28202 ,  H01L21/28211 ,  H01L29/1054 ,  H01L29/51 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66477 ,  H01L29/665 ,  H01L29/7833 ,  H01L29/7842 ,  Y10S438/933

Abstract: A method of manufacturing an integrated circuit includes providing an amorphous semiconductor material including germanium, annealing the amorphous semiconductor material, and doping to form a source location and a drain location. The semiconductor material containing germanium can increase the charge mobility associated with the transistor.

Abstract translation: 制造集成电路的方法包括提供包括锗的非晶半导体材料，退火非晶半导体材料和掺杂以形成源极位置和漏极位置。 含锗的半导体材料可以增加与晶体管相关的电荷迁移率。

公开(公告)号：US06716686B1

公开(公告)日：2004-04-06

申请号：US10613997

申请日：2003-07-08

Applicant: Matthew S. Buynoski ,  Judy Xilin An ,  Bin Yu

Inventor： Matthew S. Buynoski ,  Judy Xilin An ,  Bin Yu

IPC: H01L2100

CPC classification number: H01L29/785 ,  H01L29/42384 ,  H01L29/66795 ,  H01L29/78603 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method for forming one or more FinFET devices includes forming a source region and a drain region in an oxide layer, where the oxide layer is disposed on a substrate, and etching the oxide layer between the source region and the drain region to form a group of oxide walls and channels for a first device. The method further includes depositing a connector material over the oxide walls and channels for the first device, forming a gate mask for the first device, removing the connector material from the channels, depositing channel material in the channels for the first device, forming a gate dielectric for first device over the channels, depositing a gate material over the gate dielectric for the first device, and patterning and etching the gate material to form at least one gate electrode for the first device.

Abstract translation: 用于形成一个或多个FinFET器件的方法包括在氧化物层中形成源极区域和漏极区域，其中氧化物层设置在衬底上，并且蚀刻源极区域和漏极区域之间的氧化物层以形成基团 的第一装置的氧化物壁和通道。 该方法还包括在第一器件的氧化物壁和通道上沉积连接器材料，形成用于第一器件的栅极掩模，从通道移除连接器材料，将沟道材料沉积在第一器件的通道中，形成栅极 在沟道上的第一器件的电介质，在第一器件的栅极电介质上沉积栅极材料，以及图案化和蚀刻栅极材料以形成用于第一器件的至少一个栅电极。

公开(公告)号：US06689671B1

公开(公告)日：2004-02-10

申请号：US10151946

申请日：2002-05-22

Applicant: Bin Yu ,  Derick J. Wristers

Inventor： Bin Yu ,  Derick J. Wristers

IPC: H01L2120

CPC classification number: H01L29/6659 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/0251 ,  H01L21/02532 ,  H01L21/02667 ,  H01L21/26506 ,  H01L21/26513 ,  H01L29/78687

Abstract: A method of manufacturing a semiconductor device, comprising steps of: (a) providing a semiconductor substrate comprising a strained lattice semiconductor layer at an upper surface thereof and having a pre-selected amount of lattice strain; (b) forming a device structure in the semiconductor substrate by a process comprising forming at least one amorphous region in at least one portion of the strained lattice semiconductor layer; and (c) thermal annealing at a minimum temperature sufficient to effect epitaxial re-crystallization of the at least one amorphous region to re-form a strained lattice semiconductor layer having substantially the pre-selected amount of lattice strain, whereby strain relaxation of the strained lattice semiconductor arising from thermal annealing is substantially eliminated or minimized.

Abstract translation: 一种制造半导体器件的方法，包括以下步骤：（a）在其上表面提供包括应变晶格半导体层并具有预选量的晶格应变的半导体衬底;（b）在 半导体衬底，其包括在应变晶格半导体层的至少一部分中形成至少一个非晶区; 和（c）在足以实现所述至少一个非晶区域的外延再结晶的最小温度下的热退火以重新形成具有基本上预选量的晶格应变的应变晶格半导体层，由此应变松弛 基本消除或最小化由热退火产生的晶格半导体。

公开(公告)号：US06680233B2

公开(公告)日：2004-01-20

申请号：US09974167

申请日：2001-10-09

Applicant: Bin Yu ,  Qi Xiang ,  HaiHong Wang

Inventor： Bin Yu ,  Qi Xiang ,  HaiHong Wang

IPC: H01L21336

CPC classification number: H01L29/4983 ,  H01L29/6653 ,  H01L29/6659

Abstract: A semiconductor device and method of manufacture. A liner composed of a high-K material having a relative permittivity of greater than 10 is formed adjacent at least the sidewalls of a gate. Sidewall spacers are formed adjacent the gate and spaced apart from the gate by the liner. The liner can be removed using an etch process that has substantially no reaction with a gate dielectric of the gate.

Abstract translation: 半导体器件及其制造方法。 由栅极的至少侧壁形成由相对介电常数大于10的高K材料构成的衬垫。 侧壁间隔件形成在门附近并且通过衬套与门隔开。 可以使用与栅极的栅极电介质基本上没有反应的蚀刻工艺来去除衬里。