公开(公告)号：US20190317912A1

公开(公告)日：2019-10-17

申请号：US16365535

申请日：2019-03-26

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Kishore Kasamsetty

IPC: G06F13/40 ,  G06F13/16 ,  G06F12/02 ,  G11C5/02 ,  G06F13/42 ,  G06F12/00 ,  G06F3/06

Abstract: A multi-chip package includes a logic integrated circuit (IC) die formed with plural memory controller circuits, a first memory IC die and a second memory IC die. The second memory IC die is mounted to the first memory IC die. The first memory IC die and the logic IC die are mounted to one another. The logic IC die includes a serial link interface for coupling to multiple serial links. The first memory die includes a first memory group accessed by a first one of the plural memory controller circuits, and a second memory group accessed by a second one of the plural memory controller circuits.

公开(公告)号：US20190266112A1

公开(公告)日：2019-08-29

申请号：US16290346

申请日：2019-03-01

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Abhijit Abhyankar ,  Suresh Rajan

IPC: G06F13/16 ,  G06F13/00 ,  G06F13/42

Abstract: A memory controller and buffers on memory modules each operate in two modes, depending on the type of motherboard through which the controller and modules are connected. In a first mode, the controller transmits decoded chip-select signals independently to each module, and the motherboard data channel uses multi-drop connections to each module. In a second mode, the motherboard has point-to-point data channel and command address connections to each of the memory modules, and the controller transmits a fully encoded chip-select signal group to each module. The buffers operate modally to correctly select ranks or partial ranks of memory devices on one or more modules for each transaction, depending on the mode.

公开(公告)号：US10378967B1

公开(公告)日：2019-08-13

申请号：US15794280

申请日：2017-10-26

Applicant: Rambus Inc.

Inventor： Thomas Vogelsang ,  Frederick A. Ware

IPC: H03K19/0175 ,  G05F3/24 ,  G01K7/01 ,  G05F1/56

Abstract: During operation of an IC component within a first range of temperatures, a first bias voltage is applied to a first substrate region disposed adjacent a first plurality of transistors to effect a first threshold voltage for the first plurality of transistors. During operation of the IC component within a second range of temperatures that is distinct from and lower than the first range of temperatures, a second bias voltage is applied to the first substrate region to effect a second threshold voltage for the first plurality of transistors that is at least as low as the first threshold voltage.

公开(公告)号：US20190164588A1

公开(公告)日：2019-05-30

申请号：US16097579

申请日：2017-05-03

Applicant: RAMBUS INC.

Inventor： Frederick A. Ware ,  John Eric Linstadt ,  Brent Steven Haukness ,  Kenneth L. Wright ,  Thomas Vogelsang

IPC: G11C11/403 ,  G11C11/406 ,  G11C11/409 ,  G11C11/408

Abstract: A memory component includes a first memory bank. The first memory bank has a plurality of sub-arrays having sub-rows of memory elements. The memory component includes a write driver, coupled to the first memory bank, to perform a write operation of an entire sub-row of a sub-array. To perform the write operation, the write driver is to load a burst of write data to the memory bank. The memory bank may then activate a plurality of sense amplifiers associated with a plurality of memory elements of the entire sub-row to load the burst of write data to the plurality of sense amplifiers.

公开(公告)号：US10262750B2

公开(公告)日：2019-04-16

申请号：US15393634

申请日：2016-12-29

Applicant: RAMBUS INC.

Inventor： Thomas Vogelsang ,  William Ng ,  Frederick A. Ware

IPC: G01R31/28 ,  G11C29/02 ,  H01L21/66 ,  H01L25/065 ,  G11C8/10 ,  G11C29/04 ,  G11C5/02 ,  G11C5/06

Abstract: Embodiments generally relate to integrated circuit devices having through silicon vias (TSVs). In one embodiment, an integrated circuit (IC) device includes a field of TSVs and an address decoder that selectably couples at least one of the TSVs to at least one of a test input and a test evaluation circuit. In another embodiment, a method includes selecting one or more TSVs from a field of TSVs in at least one IC device, and coupling each selected TSV to at least one of a test input and a test evaluation circuit.

公开(公告)号：US10248358B2

公开(公告)日：2019-04-02

申请号：US15990211

申请日：2018-05-25

Applicant: RAMBUS INC.

Inventor： Frederick A. Ware ,  Thomas Vogelsang

IPC: G06F3/06 ,  G11C7/10 ,  G11C29/02 ,  G06F11/10 ,  G11C29/04

Abstract: An memory component includes a memory bank and a command interface to receive a read-modify-write command, having an associated read address indicating a location in the memory bank and to either access read data from the location in the memory bank indicated by the read address after an adjustable delay period transpires from a time at which the read-modify-write command was received or to overlap multiple read-modify-write commands. The memory component further includes a data interface to receive write data associated with the read-modify-write command and an error correction circuit to merge the received write data with the read data to form a merged data and write the merged data to the location in the memory bank indicated by the read address.

公开(公告)号：US10248342B2

公开(公告)日：2019-04-02

申请号：US16145931

申请日：2018-09-28

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Robert E. Palmer ,  John W. Poulton

IPC: G06F12/00 ,  G06F13/00 ,  G06F3/06 ,  G11C11/406 ,  G11C7/02 ,  G06Q20/00 ,  G06Q10/00 ,  G06F13/16

Abstract: A system includes a memory controller and a memory device having a command interface and a plurality of memory banks, each with a plurality of rows of memory cells. The memory controller transmits an auto-refresh command to the memory device. Responsive to the auto-refresh command, during a first time interval, the memory device performs refresh operations to refresh the memory cells and the command interface of the memory device is placed into a calibration mode for the duration of the first time interval. Concurrently, during at least a portion of the first time interval, the memory controller performs a calibration of the command interface of the memory device. The auto-refresh command may specify an order in which memory banks of the memory device are to be refreshed, such that the memory device sequentially refreshes a respective row in the plurality of memory banks in the specified bank order.

公开(公告)号：US20190095264A1

公开(公告)日：2019-03-28

申请号：US16120819

申请日：2018-09-04

Applicant: Rambus Inc.

Inventor： Ely K. Tsern ,  Mark A. Horowitz ,  Frederick A. Ware

IPC: G06F11/07 ,  G06F11/00 ,  G06F11/10 ,  H04L1/00 ,  G06F3/06 ,  H04L1/08 ,  H04L1/18 ,  G11C29/52 ,  G06F11/14 ,  H03M13/03 ,  G06F11/20

Abstract: A memory system includes a link having at least one signal line and a controller. The controller includes at least one transmitter coupled to the link to transmit first data, and a first error protection generator coupled to the transmitter. The first error protection generator dynamically adds an error detection code to at least a portion of the first data. At least one receiver is coupled to the link to receive second data. A first error detection logic determines if the second data received by the controller contains at least one error and, if an error is detected, asserts a first error condition. The system includes a memory device having at least one memory device transmitter coupled to the link to transmit the second data. A second error protection generator coupled to the memory device transmitter dynamically adds an error detection code to at least a portion of the second data.

公开(公告)号：US10236051B2

公开(公告)日：2019-03-19

申请号：US15666496

申请日：2017-08-01

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Ely K. Tsern ,  Richard E. Perego ,  Craig E. Hampel

IPC: G11C11/24 ,  G11C11/4076 ,  G11C7/10 ,  G06F13/16 ,  G06F13/40 ,  G11C5/06 ,  G11C29/02 ,  G11C29/50 ,  G11C8/18 ,  G11C7/22 ,  G06F1/10 ,  G11C11/409 ,  G11C11/4096 ,  G06F1/06 ,  G06F1/12 ,  G06F3/06 ,  G11C7/04

Abstract: A memory controller component includes transmit circuitry and adjusting circuitry. The transmit circuitry transmits a clock signal and write data to a DRAM, the write data to be sampled by the DRAM using a timing signal. The adjusting circuitry adjusts transmit timing of the write data and of the timing signal such that an edge transition of the timing signal is aligned with an edge transition of the clock signal at the DRAM.

公开(公告)号：US10235242B2

公开(公告)日：2019-03-19

申请号：US15260880

申请日：2016-09-09

Applicant: Rambus Inc.

Inventor： Kenneth L. Wright ,  Frederick A. Ware

IPC: G06F11/00 ,  G06F11/14 ,  H01L23/00 ,  G06F3/06 ,  G06F13/16 ,  G06F13/40

Abstract: A memory system includes dynamic random-access memory (DRAM) components that include interconnected and redundant component data interfaces. The redundant interfaces facilitate memory interconnect topologies that accommodate considerably more DRAM components per memory channel than do traditional memory systems, and thus offer considerably more memory capacity per channel, without concomitant reductions in signaling speeds. The memory components can be configured to route data around defective data connections to maintain full capacity and continue to support memory transactions.