公开(公告)号：US10210080B2

公开(公告)日：2019-02-19

申请号：US15050246

申请日：2016-02-22

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Ely K. Tsern

IPC: G06F12/00 ,  G06F13/00 ,  G06F13/28 ,  G06F12/02 ,  G06F12/0804 ,  G06F12/08 ,  G06F12/0802 ,  G06F12/0891 ,  G06F12/1009

Abstract: A memory system includes nonvolatile physical memory, such as flash memory, that exhibits a wear mechanism asymmetrically associated with write operations. A relatively small cache of volatile memory reduces the number of writes, and wear-leveling memory access methods distribute writes evenly over the nonvolatile memory.

公开(公告)号：US20190043555A1

公开(公告)日：2019-02-07

申请号：US16032575

申请日：2018-07-11

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Brent Haukness

IPC: G11C11/406 ,  G06F13/16

CPC classification number: G11C11/40611 ,  G06F13/1636 ,  G11C11/406 ,  G11C11/40615 ,  G11C11/40618 ,  G11C2211/4067 ,  Y02D10/14

Abstract: The present embodiments provide a system that supports self-refreshing operations in a memory device. During operation, the system transitions the memory device from an auto-refresh state, wherein a memory controller controls refreshing operations for the memory device, to a self-refresh state, wherein the memory device controls the refreshing operations. While the memory device is in the self-refresh state, the system sends progress information for the refreshing operations from the memory device to the memory controller. Next, upon returning from the self-refresh state to the auto-refresh state, the system uses the progress information received from the memory device to control the sequencing of subsequent operations by the memory controller.

公开(公告)号：US10199089B2

公开(公告)日：2019-02-05

申请号：US15876539

申请日：2018-01-22

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  John Eric Linstadt ,  Thomas Vogelsang

IPC: G11C8/00 ,  G11C11/4093 ,  G11C11/4094 ,  G11C11/4076 ,  G11C11/4097

Abstract: A memory stack comprises at least two memory components. The memory components have a first data link interface and are to transmit signals on a data link coupled to the first data link interface at a first voltage level. A buffer component has a second data link interface coupled to the data link. The buffer component is to receive signals on the second data link interface at the first voltage level. A level shifting latch produces a second voltage level in response to receiving the signals at the second data link interface, where the second voltage level is higher than the first voltage level.

公开(公告)号：US20190034099A1

公开(公告)日：2019-01-31

申请号：US16145931

申请日：2018-09-28

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Robert E. Palmer ,  John W. Poulton

IPC: G06F3/06 ,  G06Q20/00 ,  G11C11/406 ,  G11C7/02 ,  G06Q10/00 ,  G06F13/16

Abstract: A system includes a memory controller and a memory device having a command interface and a plurality of memory banks, each with a plurality of rows of memory cells. The memory controller transmits an auto-refresh command to the memory device. Responsive to the auto-refresh command, during a first time interval, the memory device performs refresh operations to refresh the memory cells and the command interface of the memory device is placed into a calibration mode for the duration of the first time interval. Concurrently, during at least a portion of the first time interval, the memory controller performs a calibration of the command interface of the memory device. The auto-refresh command may specify an order in which memory banks of the memory device are to be refreshed, such that the memory device sequentially refreshes a respective row in the plurality of memory banks in the specified bank order.

公开(公告)号：US20180341432A1

公开(公告)日：2018-11-29

申请号：US15990211

申请日：2018-05-25

Applicant: RAMBUS INC.

Inventor： Frederick A. Ware ,  Thomas Vogelsang

IPC: G06F3/06 ,  G06F11/10 ,  G11C7/10

CPC classification number: G06F3/0659 ,  G06F3/0604 ,  G06F3/0619 ,  G06F3/0638 ,  G06F3/0673 ,  G06F11/1076 ,  G11C7/1006 ,  G11C7/1009 ,  G11C7/1087 ,  G11C7/109 ,  G11C7/1093 ,  G11C29/023 ,  G11C29/028 ,  G11C2029/0411 ,  G11C2207/107

Abstract: An memory component includes a memory bank and a command interface to receive a read-modify-write command, having an associated read address indicating a location in the memory bank and to either access read data from the location in the memory bank indicated by the read address after an adjustable delay period transpires from a time at which the read-modify-write command was received or to overlap multiple read-modify-write commands. The memory component further includes a data interface to receive write data associated with the read-modify-write command and an error correction circuit to merge the received write data with the read data to form a merged data and write the merged data to the location in the memory bank indicated by the read address.

公开(公告)号：US20180210779A1

公开(公告)日：2018-07-26

申请号：US15855385

申请日：2017-12-27

Applicant: Rambus Inc.

Inventor： Yuanlong Wang ,  Frederick A. Ware

IPC: G06F11/07 ,  H03M13/00 ,  H03M13/09 ,  G06F11/10

CPC classification number: G06F11/0727 ,  G06F3/0619 ,  G06F3/064 ,  G06F3/0679 ,  G06F11/073 ,  G06F11/0751 ,  G06F11/076 ,  G06F11/0793 ,  G06F11/10 ,  G06F11/1004 ,  G06F11/1008 ,  G06F11/1044 ,  G06F11/1068 ,  G06F11/1402 ,  G06F13/4286 ,  H03M13/09 ,  H03M13/29 ,  H03M13/2906 ,  H03M13/611 ,  H04L1/0003 ,  H04L1/0008 ,  H04L1/0061 ,  H04L1/08 ,  H04L1/1867 ,  H04L2001/0093

Abstract: A memory device includes a first interface that is to couple to a bidirectional link and a second interface to couple to a unidirectional link. An encoder generates first error-detection information corresponding to write data received via the bidirectional link for a write operation. An encoder generates second error-detection information corresponding to read data transmitted via the bidirectional link for a read operation. A transmitter coupled to the unidirectional link transmits the both the first and second error-detection information. A controller may receive the first and second error-detection information. Based on at least one of the first and second error-detection information, the controller may command the memory device to retry an operation.

公开(公告)号：US20180196462A1

公开(公告)日：2018-07-12

申请号：US15863703

申请日：2018-01-05

Applicant: Rambus Inc.

Inventor： Frederick A. Ware

IPC: G06F1/08 ,  G11C7/22 ,  G11C7/10 ,  G11C7/04 ,  G06F1/04 ,  G11C7/02 ,  G06F1/10 ,  G06F1/06 ,  G06F1/12

CPC classification number: G06F1/08 ,  G06F1/04 ,  G06F1/06 ,  G06F1/10 ,  G06F1/12 ,  G11C7/02 ,  G11C7/04 ,  G11C7/1066 ,  G11C7/1093 ,  G11C7/222

Abstract: The disclosed embodiments relate to a memory system that generates a multiplied timing signal from a reference timing signal. During operation, the system receives a reference timing signal. Next, the system produces a multiplied timing signal from the reference timing signal by generating a burst comprising multiple timing events for each timing event in the reference timing signal, wherein consecutive timing events in each burst of timing events are separated by a bit time. Then, as the reference clock frequency changes, the interval between bursts of timing events changes while the bit time remains substantially constant.

公开(公告)号：US09983830B2

公开(公告)日：2018-05-29

申请号：US15022176

申请日：2014-09-23

Applicant: RAMBUS INC.

Inventor： Frederick A. Ware ,  Thomas Vogelsang

IPC: G06F3/06 ,  G11C7/10 ,  G11C29/02 ,  G06F11/10 ,  G11C29/04

CPC classification number: G06F3/0659 ,  G06F3/0604 ,  G06F3/0619 ,  G06F3/0638 ,  G06F3/0673 ,  G06F11/1076 ,  G11C7/1006 ,  G11C7/1009 ,  G11C7/1087 ,  G11C7/109 ,  G11C7/1093 ,  G11C29/023 ,  G11C29/028 ,  G11C2029/0411 ,  G11C2207/107

Abstract: An memory component includes a memory bank and a command interface to receive a read-modify-write command, having an associated read address indicating a location in the memory bank and to either access read data from the location in the memory bank indicated by the read address after an adjustable delay period transpires from a time at which the read-modify-write command was received or to overlap multiple read-modify-write commands. The memory component further includes a data interface to receive write data associated with the read-modify-write command and an error correction circuit to merge the received write data with the read data to form a merged data and write the merged data to the location in the memory bank indicated by the read address.

公开(公告)号：US20180145670A1

公开(公告)日：2018-05-24

申请号：US15824892

申请日：2017-11-28

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Ely Tsern ,  Brian S. Leibowitz ,  Jared Zerbe

IPC: H03K5/13 ,  G11C29/02 ,  G11C7/22 ,  G11C7/10 ,  G06F13/16 ,  G11C7/04 ,  G06F13/42 ,  G06F13/00

Abstract: An integrated circuit includes a delay circuit and first and second interface circuits. The delay circuit delays a first timing signal by an internal delay to generate an internal timing signal. The first interface circuit communicates data to an external device in response to the internal timing signal. The second interface circuit transmits an external timing signal for capturing the data in the external device. An external delay is added to the external timing signal in the external device to generate a delayed external timing signal. The delay circuit sets the internal delay based on a comparison between the delayed external timing signal and a calibration signal transmitted by the first interface circuit.

公开(公告)号：US20180137067A1

公开(公告)日：2018-05-17

申请号：US15808595

申请日：2017-11-09

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  John Eric Linstadt ,  Kenneth Lee Wright

IPC: G06F13/16 ,  G06F13/28

Abstract: A memory module comprises an address buffer circuit, a command/address channel, and a plurality of memory components controlled by the address buffer circuit via the command/address channel. At least one memory component comprises a plurality of data ports, a memory core to store data, and a data interface. The data interface is capable of transferring data between the memory core and the data ports. The data interface supports a first data width mode in which the data interface transfers data at a first bit width and a first burst length via the data ports. The data interface also supports a second data width mode in which the data interface transfers data at a second bit width and second burst length via the data ports. The first bit width is greater than the second bit width and the first burst length is shorter than the second burst length.