公开(公告)号：US20220100249A1

公开(公告)日：2022-03-31

申请号：US17127681

申请日：2020-12-18

Applicant: Advanced Micro Devices, Inc.

Inventor： Sriram Sambamurthy ,  Sriram Sundaram ,  Indrani Paul ,  Larry David Hewitt ,  Anil Harwani ,  Aaron Joseph Grenat ,  Dana Glenn Lewis ,  Leonardo Piga ,  Wonje Choi ,  Karthik Rao

IPC: G06F1/28 ,  G06F1/30 ,  G01R31/40

Abstract: A system and method for updating power supply voltages due to variations from aging are described. A functional unit includes a power supply monitor capable of measuring power supply variations in a region of the functional unit. An age counter measures an age of the functional unit. A control unit notifies the power supply monitor to measure an operating voltage reference. When the control unit receives a measured operating voltage reference, the control unit determines an updated age of the region different from the current age based on the measured operating voltage reference. The control unit updates the age counter with the corresponding age, which is younger than the previous age in some cases due to the region not experiencing predicted stress and aging. The control unit is capable of determining a voltage adjustment for the operating voltage reference based on an age indicated by the age counter.

公开(公告)号：US20220093504A1

公开(公告)日：2022-03-24

申请号：US17030830

申请日：2020-09-24

Applicant: Advanced Micro Devices, Inc.

Inventor： Richard T. Schultz ,  John J. Wuu

IPC: H01L23/528 ,  H01L27/11 ,  H01L23/522 ,  G11C11/418 ,  G11C11/419 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786

Abstract: A layout for a 6T SRAM cell is disclosed. The cell layout takes a conventional 6T SRAM cell layout and restructures the layout into a more square cell layout with a single p-channel and a single n-channel across the width of the cell. Restructuring the cell layout reduces the height of wordlines and allows dual wordlines to be placed in the cell to reduce wordline resistance in the cell. Dual pairs of bitlines may also be placed in separate metal layers in the cell layout to reduce bitline resistance.

公开(公告)号：US20220091980A1

公开(公告)日：2022-03-24

申请号：US17031706

申请日：2020-09-24

Applicant: Advanced Micro Devices, Inc.

Inventor： Onur Kayiran ,  Yasuko Eckert ,  Mark Henry Oskin ,  Gabriel H. Loh ,  Steven E. Raasch ,  Maxim V. Kazakov

IPC: G06F12/0811 ,  G06F12/084 ,  G06F12/0877 ,  G06F13/16 ,  G06F11/30

Abstract: A system and method for efficiently processing memory requests are described. A computing system includes multiple compute units, multiple caches of a memory hierarchy and a communication fabric. A compute unit generates a memory access request that misses in a higher level cache, which sends a miss request to a lower level shared cache. During servicing of the miss request, the lower level cache merges identification information of multiple memory access requests targeting a same cache line from multiple compute units into a merged memory access response. The lower level shared cache continues to insert information into the merged memory access response until the lower level shared cache is ready to issue the merged memory access response. An intermediate router in the communication fabric broadcasts the merged memory access response into multiple memory access responses to send to corresponding compute units.

公开(公告)号：US20220091880A1

公开(公告)日：2022-03-24

申请号：US17031424

申请日：2020-09-24

Applicant: Advanced Micro Devices, Inc.

Inventor： Alexandru Dutu ,  Marcus Nathaniel Chow ,  Matthew D. Sinclair ,  Bradford M. Beckmann ,  David A. Wood

IPC: G06F9/48 ,  G06F9/38 ,  G06F9/54

Abstract: Techniques for executing workgroups are provided. The techniques include executing, for a first workgroup of a first kernel dispatch, a workgroup dependency instruction that includes an indication to prioritize execution of a second workgroup of a second kernel dispatch, and in response to the workgroup dependency instruction, dispatching the second workgroup of the second kernel dispatch prior to dispatching a third workgroup of the second kernel dispatch, wherein no workgroup dependency instruction including an indication to prioritize execution of the third workgroup has been executed.

公开(公告)号：US20220091822A1

公开(公告)日：2022-03-24

申请号：US17028723

申请日：2020-09-22

Applicant: Advanced Micro Devices, Inc.

Inventor： Ravinder Reddy Rachala ,  Stephen Victor Kosonocky ,  Miguel Rodriguez

IPC: G06F7/544 ,  H03K21/08

Abstract: A multiply-accumulate computation is performed using digital logic circuits. To perform the computation, a plurality of target signals are received at a respective plurality of ripple counters. The counter outputs of the respective ripple counters are scaled by setting stop count values. Counter outputs of the respective ripple counters are adjusted with respective constant values by setting counter reset values at the respective ripple counters. Each count pulses of the target signals for an adjusted period. The count values of the ripple counters are summed. The results may be used to calculate an average value for an adaptive voltage and frequency scaling process.

公开(公告)号：US20220091661A1

公开(公告)日：2022-03-24

申请号：US17029042

申请日：2020-09-23

Applicant: Advanced Micro Devices, Inc.

Inventor： Martin McAfee ,  David L. Wigton

IPC: G06F1/3296 ,  G06F1/28 ,  G06F1/3287

Abstract: A method of operating a multiphase power supply includes identifying a least efficient phase of a plurality of phases in the multiphase power supply based on a comparison of a pulse width for each phase in the plurality of phases, and decreasing an amount of power supplied to a load by the identified least efficient phase.

公开(公告)号：US20220091653A1

公开(公告)日：2022-03-24

申请号：US17030324

申请日：2020-09-23

Applicant: Advanced Micro Devices, Inc.

Inventor： Mahesh Subramony ,  David Suggs ,  Michael T. Clark ,  Matthew M. Crum

IPC: G06F1/3206 ,  G06F1/28 ,  G06F1/3287

Abstract: A method of operating a processing unit includes, in response to detecting that the processing unit is operating in a voltage limited state, calculating a set of headroom values by calculating a headroom value for each operational constraint in a set of operational constraints of the processing unit, based on the calculated set of headroom values, selecting from a set of performance features a subset of one or more performance features for enabling in the processing unit, and enabling the selected subset of performance features in the processing unit.

公开(公告)号：US11281280B2

公开(公告)日：2022-03-22

申请号：US16876325

申请日：2020-05-18

Applicant: Advanced Micro Devices, Inc. ,  ATI Technologies ULC

Inventor： Benjamin Tsien ,  Michael J. Tresidder ,  Ivan Yanfeng Wang ,  Kevin M. Lepak ,  Ann Ling ,  Richard M. Born ,  John P. Petry ,  Bryan P. Broussard ,  Eric Christopher Morton

IPC: G06F1/32 ,  G06F1/3206 ,  G06F1/3287 ,  G06F1/3234

Abstract: Systems, apparatuses, and methods for reducing chiplet interrupt latency are disclosed. A system includes one or more processing nodes, one or more memory devices, a communication fabric coupled to the processing unit(s) and memory device(s) via link interfaces, and a power management unit. The power management unit manages the power states of the various components and the link interfaces of the system. If the power management unit detects a request to wake up a given component, and the link interface to the given component is powered down, then the power management unit sends an out-of-band signal to wake up the given component in parallel with powering up the link interface. Also, when multiple link interfaces need to be powered up, the power management unit powers up the multiple link interfaces in an order which complies with voltage regulator load-step requirements while minimizing the latency of pending operations.

公开(公告)号：US11275430B2

公开(公告)日：2022-03-15

申请号：US16115420

申请日：2018-08-28

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Greg Sadowski ,  Ying Chen

IPC: G06F1/32 ,  G06F1/3296 ,  G06F9/50 ,  G06F1/3287

Abstract: An apparatus includes a plurality of registers to store sets of state information that represent a state history of a processing unit. The apparatus also includes a power management advisor (PMA) to generate a signal based on the sets of state information, wherein the signal indicates a probability that a power state transition of the processing unit achieves a target outcome. In some cases, the signal is provided to a power management controller including hardware circuitry that initiates a power state transition of the processing unit based on the signal and inputs to the power management controller that represent a subset of the state information corresponding to a current power state of the processing unit.

公开(公告)号：US20220075624A1

公开(公告)日：2022-03-10

申请号：US17012833

申请日：2020-09-04

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Ashok T. VENKATACHAR ,  Robert COHEN ,  Steven R. HAVLIR ,  Aparna Chandrashekhar MANDKE ,  Tzu-Wei LIN ,  Bhawna NAYAK

IPC: G06F9/38 ,  G06F9/30 ,  G06F9/48 ,  G06F12/1027

Abstract: Branch prediction circuitry predicts an outcome of a branch instruction. A pipeline circuitry processes instructions along a first path from a predicted branch of the branch instruction. The instructions along the first path are processed concurrently with processing instructions along a second path from an unpredicted branch of the branch instruction. Information representing the state of the second portion while processing the second path is stored in one or more buffers. The instructions are processed along the second path using the information stored in the buffers in response to a misprediction of the outcome of the branch instruction. In some cases, the branch prediction circuitry determines a confidence level for the predicted outcome and the instructions along the second path from the unpredicted branch are processed in response to the confidence level being below a threshold confidence.