公开(公告)号：US20180359227A1

公开(公告)日：2018-12-13

申请号：US15620270

申请日：2017-06-12

Applicant: Seagate Technology LLC

Inventor： Jon D. Trantham ,  Mark A. Gaertner ,  Monty Aaron Forehand ,  Paul Michael Wiggins

IPC: H04L29/06 ,  G06F12/14

CPC classification number: H04L63/0457 ,  G06F21/6218 ,  G06F2221/2143 ,  H04L63/061

Abstract: A method includes adding a key version tag to an encryption key store that stores encryption keys. The key version tag is inserted into a data stream. The data stream including the key version tag is written to media. The data in the data stream is erased by scrambling the encryption keys and incrementing the key version tag in the encryption store by a digit. The data stream is replaced with a replacement data pattern when the key version tag stored in the encryption store and the key version tag located in the data stream mismatch.

公开(公告)号：US10153782B2

公开(公告)日：2018-12-11

申请号：US15198533

申请日：2016-06-30

Applicant: Seagate Technology LLC

Inventor： Yu Cai ,  Yunxiang Wu ,  Erich F. Haratsch

IPC: H03M13/11 ,  H03M13/35 ,  G06F11/10 ,  H03M13/37 ,  H03M13/00

Abstract: A method of characterizing a distribution of a maximum number of errors that first cause uncorrectable error correction code failure for hard low density parity check codes includes selecting a low density parity check code, generating encoded data with the low density parity check code and writing the encoded data to a number of memory blocks, reading the encoded data from the number of memory blocks and determining any pages having a first uncorrectable error correction code failure, determining a number of raw bit errors for each page having a first uncorrectable error correction code failure, incrementing an error count value corresponding to each of the numbers of raw bit errors determined, and repeating the generating, reading, determining, and incrementing steps for a predetermined range of values of a predetermined reliability statistic of the memory blocks.

公开(公告)号：US10152997B1

公开(公告)日：2018-12-11

申请号：US15660832

申请日：2017-07-26

Applicant: Seagate Technology LLC

Inventor： Alfredo Sam Chu ,  Todd Michael Lammers ,  Thomas Lee Schick ,  Robert Matousek

IPC: G11B5/09 ,  G11B20/10 ,  G11B5/60

Abstract: Systems and methods of laser bias calibration are presented. A preamplifier circuit may configure a laser current supplied to a laser emitter to be a first laser current of the plurality of laser currents during the writing of one or more first sectors. The preamplifier may further detect one or more gaps in a write power signal while the laser current of the laser emitter is configured to be the first laser current. In response to the detection of the one or more gaps in the write power signal, the preamplifier may configure the laser current supplied to the laser emitter to be a second laser current of the plurality of laser currents during the writing of one or more second sectors. The preamplifier circuit may be utilized in a heat assisted magnetic recording device.

公开(公告)号：US10152457B1

公开(公告)日：2018-12-11

申请号：US15334167

申请日：2016-10-25

Applicant: Seagate Technology LLC

Inventor： Jason Vincent Bellorado ,  Marcus Marrow ,  Zheng Wu

IPC: G06F17/10 ,  G06F17/17 ,  G06F17/11

Abstract: An apparatus may include a circuit including a filter configured to update one or more adaptive coefficients of the filter based on an error signal. Further, the circuit may update a constrained coefficient of the filter based on the one or more adaptive coefficients, the constrained coefficient and a desired value. Moreover, the circuit may generate a sample of a sample sequence based on the one or more adaptive coefficients and the updated constrained coefficient, the error signal being based on the sample sequence.

公开(公告)号：US10152249B2

公开(公告)日：2018-12-11

申请号：US15272240

申请日：2016-09-21

Applicant: Seagate Technology LLC

Inventor： Jon David Trantham

IPC: G06F11/00 ,  G06F3/06 ,  G06F11/10 ,  G11C29/52 ,  H03M13/09

Abstract: The present disclosure provides a data storage system including a data memory device and controller having interface error detection and handling logic. In one example, a solid-state data memory device is provided and includes a semiconductor package. A memory array is provided in the semiconductor package and an interface is provided that is communicatively couplable to a device bus for receiving data to be stored to the memory array. An error detection component is provided in the semiconductor package and is associated with the interface of the solid-state data memory device. The error detection component is configured to detect errors occurring on data received at the interface prior to the data being stored to the memory array.

公开(公告)号：US10152105B2

公开(公告)日：2018-12-11

申请号：US14676612

申请日：2015-04-01

Applicant: Seagate Technology LLC

Inventor： Phil Jurey ,  Jerry Dallmann ,  John Shaw ,  Tony Pronozuk ,  Steve Williams

IPC: G06F1/26 ,  G06F1/28 ,  G06F1/32 ,  G06F3/06 ,  G06F11/20

Abstract: A mass data storage system includes a number of communicatively coupled storage drives powered by one or more power supplies. A common controller selectively connects power and a data signal to a desired storage drive via instructions within a control signal received by the common controller. The common controller includes switches that selectively connect power to a voice coil motor and a spindle motor of the desired storage drive. The common controller further includes a switch that controls the preamp of the desired storage drive and a switch that controls the flow of data to and from the desired storage drive.

公开(公告)号：US20180351582A1

公开(公告)日：2018-12-06

申请号：US15610744

申请日：2017-06-01

Applicant: Seagate Technology, LLC

Inventor： Timothy Canepa

IPC: H03M13/35 ,  H03M13/00 ,  G06F3/06 ,  G06F12/02 ,  H03M13/11 ,  H03M13/29 ,  G06F11/10 ,  G11C29/52

CPC classification number: H03M13/353 ,  G06F3/0608 ,  G06F3/0652 ,  G06F3/0688 ,  G06F11/1068 ,  G06F12/0246 ,  G06F2212/2022 ,  G06F2212/7205 ,  G11C29/52 ,  H03M13/1105 ,  H03M13/2906 ,  H03M13/6577

Abstract: Method and apparatus for managing data in a memory, such as a flash memory. In accordance with some embodiments, a solid-state non-volatile memory (NVM) has a total user data storage capacity and an overprovisioning (OP) level. A control circuit writes parity data sets to the NVM each having a plurality of code words and an outer code. The code words include inner codes at an inner code rate to detect and correct read errors in a user data payload. The outer code includes parity data at an outer code rate to detect and correct read errors in the code words. A code adjustment circuit increases the inner code rate to compensate for a measured parameter associated with the NVM, and decreases the outer code rate to maintain the data capacity and OP levels above selected thresholds.

公开(公告)号：US20180350447A1

公开(公告)日：2018-12-06

申请号：US15607784

申请日：2017-05-30

Applicant: Seagate Technology, LLC

Inventor： David S. Ebsen ,  Mark Ish ,  Timothy Canepa

IPC: G11C29/00 ,  G06F12/02 ,  G11C11/406 ,  G11C7/18 ,  G11C8/14 ,  G06F12/1045

CPC classification number: G11C29/789 ,  G06F12/0238 ,  G06F12/1054 ,  G06F12/1063 ,  G11C7/18 ,  G11C8/14 ,  G11C11/40607

Abstract: A data storage device may consist of a non-volatile memory connected to a selection module. The non-volatile memory can have a rewritable in-place memory cell that has a read-write asymmetry. The selection module can dedicate a portion of the non-volatile memory to a data map that can be self-contained along with reactively and proactively altered by the selection module.

公开(公告)号：US20180349301A1

公开(公告)日：2018-12-06

申请号：US15610815

申请日：2017-06-01

Applicant: Seagate Technology LLC

Inventor： Timothy Canepa

IPC: G06F13/16 ,  G06F13/40 ,  G11C16/10 ,  G11C16/26

Abstract: Method and apparatus for managing a non-volatile memory (NVM). In some embodiments, a memory module has a memory module electronics (MME) circuit configured to program data to and read data from solid-state non-volatile memory cells of the NVM. A controller is adapted to communicate commands and data to the MME circuit via an intervening data bus. The controller operates to reset the MME circuit by issuing a reset command to the MME circuit over the data bus, activating a decoupling circuit coupled between the data bus and a reference line at a reference voltage level to remove capacitance from the data bus resulting from the reset command, and subsequently sensing a voltage on the data bus. In some cases, multiple MME circuits and NVMs may be arranged on a plurality of flash dies which are concurrently reset by the controller.

公开(公告)号：US20180349266A1

公开(公告)日：2018-12-06

申请号：US15609198

申请日：2017-05-31

Applicant: Seagate Technology, LLC

Inventor： Timothy Canepa ,  Ryan J. Goss ,  Stephen Hanna

IPC: G06F12/02 ,  G06F3/06

CPC classification number: G06F12/0246 ,  G06F3/061 ,  G06F3/065 ,  G06F3/0655 ,  G06F3/0688 ,  G06F2212/7201

Abstract: Method and apparatus for managing data such as in a flash memory. In some embodiments, a memory module electronics (MME) circuit writes groups of user data blocks to consecutive locations within a selected section of a non-volatile memory (NVM), and concurrently writes a directory map structure as a sequence of map entries distributed among the groups of user data blocks. Each map entry stores address information for the user data blocks in the associated group and a pointer to a subsequent map entry in the sequence. A control circuit accesses a first map entry in the sequence and uses the address information and pointer in the first map entry to locate the remaining map entries and the locations of the user data blocks in the respective groups. Lossless data compression may be applied to the groups prior to writing.