公开(公告)号：US20210336044A1

公开(公告)日：2021-10-28

申请号：US17367647

申请日：2021-07-06

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Kai-Lin Lee ,  Zhi-Cheng Lee ,  Wei-Jen Chen

IPC: H01L29/778 ,  H01L29/20 ,  H01L21/02 ,  H01L21/308 ,  H01L29/66

Abstract: A method for fabricating high electron mobility transistor (HEMT) includes the steps of: forming a buffer layer on a substrate; forming a barrier layer on the buffer layer; forming a hard mask on the barrier layer; removing the hard mask to form a first recess for exposing the barrier layer; removing the hard mask adjacent to the first recess to form a second recess; and forming a p-type semiconductor layer in the first recess and the second recess.

公开(公告)号：US20210327706A1

公开(公告)日：2021-10-21

申请号：US17359634

申请日：2021-06-27

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Feng-Yi Chang ,  Fu-Che Lee ,  Yu-Cheng Tung

IPC: H01L21/027 ,  H01L21/033 ,  G03F7/26 ,  H01L27/108 ,  G03F7/16 ,  G03F7/20

Abstract: A method of manufacturing a semiconductor device includes the following steps. A first patterned photoresist layer is formed on a substrate. A second patterned photoresist layer is formed on the substrate after the first patterned photoresist layer is formed, wherein the first patterned photoresist layer and the second patterned photoresist layer are arranged alternatively. A liner is formed to cover sidewalls of the first patterned photoresist layer and the second patterned photoresist layer. The present invention also provides a semiconductor device, including a plurality of pillars being disposed on a layer, wherein the layer includes first recesses and second recesses, wherein the depths of the first recesses are less than the depths of the second recesses.

公开(公告)号：US20210320187A1

公开(公告)日：2021-10-14

申请号：US16867579

申请日：2020-05-06

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chia-Ming Kuo ,  Fu-Jung Chuang ,  Po-Jen Chuang ,  Chia-Wei Chang ,  Guan-Wei Huang ,  Chia-Yuan Chang

IPC: H01L29/66 ,  H01L29/78 ,  H01L21/28

Abstract: A method for fabricating a semiconductor device includes the steps of: providing a substrate having a NMOS region and a PMOS region; forming a first gate structure on the NMOS region and a second gate structure on the PMOS region; forming a seal layer on the first gate structure and the second gate structure; forming a first lightly doped drain (LDD) adjacent to the first gate structure; forming a second LDD adjacent to the second gate structure; and performing a soak anneal process to boost an oxygen concentration of the seal layer for reaching a saturation level.

公开(公告)号：US11139243B2

公开(公告)日：2021-10-05

申请号：US16446590

申请日：2019-06-19

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Feng-Yi Chang ,  Shih-Fang Tzou ,  Fu-Che Lee ,  Chien-Cheng Tsai ,  Feng-Ming Huang

IPC: H01L23/52 ,  H01L23/528 ,  H01L21/311 ,  H01L27/108 ,  H01L21/768 ,  H01L23/522 ,  H01L21/762 ,  H01L29/06

Abstract: A semiconductor memory device and a manufacturing method thereof are provided in the present invention. An under-cut structure is formed at an edge of a bit line contact opening in the process of forming the bit line contact opening for avoiding short problems caused by alignment shifting, and the process window of the process of forming the bit line contact opening may be improved accordingly.

公开(公告)号：US11139011B2

公开(公告)日：2021-10-05

申请号：US16556170

申请日：2019-08-29

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hui-Lin Wang ,  Yu-Ping Wang ,  Chen-Yi Weng ,  Chin-Yang Hsieh ,  Yi-Hui Lee ,  Ying-Cheng Liu ,  Yi-An Shih ,  I-Ming Tseng ,  Jing-Yin Jhang ,  Chien-Ting Lin

IPC: G11C11/16 ,  H01L27/22 ,  H01L43/02 ,  H01L43/12

Abstract: A method for forming a semiconductor structure is disclosed. A substrate having a logic device region and a memory device region is provided. A first dielectric layer is formed on the substrate. Plural memory stack structures are formed on the first dielectric layer on the memory device region. An insulating layer is formed and conformally covers the memory stack structures and the first dielectric layer. An etching back process is performed to remove a portion of the insulating layer without exposing any portion of the memory stack structures. After the etching back process, a second dielectric layer is formed on the insulating layer and completely fills the spaces between the memory stack structures.

公开(公告)号：US20210305377A1

公开(公告)日：2021-09-30

申请号：US16831850

申请日：2020-03-27

Applicant: United Microelectronics Corp.

Inventor： ZHUONA MA ,  Mengkai Zhu ,  Runshun Wang ,  Hua-Kuo Lee

IPC: H01L21/28 ,  H01L21/3213 ,  H01L21/311

Abstract: A method for fabricating a semiconductor device is provided. The method includes providing a substrate, having a cell region and a logic region and including a first conductive layer as a top layer, wherein shallow trench isolation (STI) structures are disposed in the substrate at cell region and the logic region. A first dry etching process is performed to preliminarily etch the first conductive layer and the STI structures at the cell region. A wet etching process is performed over the substrate to etch the STI structures down to a preserved height. A control gate stack is formed on the first conductive layer at the cell region. A second dry etching process is performed on a portion of the first conductive layer to form a floating gate under the control gate stack at the cell region and remove the first conductive layer at the logic region.

公开(公告)号：US20210296570A1

公开(公告)日：2021-09-23

申请号：US17338632

申请日：2021-06-03

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hui-Lin Wang ,  Po-Kai Hsu ,  Chen-Yi Weng ,  Jing-Yin Jhang ,  Yu-Ping Wang ,  Hung-Yueh Chen

IPC: H01L43/02 ,  H01L27/22 ,  H01L43/08 ,  H01L43/12

Abstract: A semiconductor device includes: a substrate comprising a magnetic tunneling junction (MTJ) region and a logic region, a MTJ on the MTJ region, a top electrode on the MTJ, a connecting structure on the top electrode, and a first metal interconnection on the logic region. Preferably, the first metal interconnection includes a via conductor on the substrate and a trench conductor, in which a bottom surface of the trench conductor is lower than a bottom surface of the connecting structure.

公开(公告)号：US20210288107A1

公开(公告)日：2021-09-16

申请号：US17336279

申请日：2021-06-01

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Wei Kuo ,  Tai-Cheng Hou ,  Yu-Tsung Lai ,  Jiunn-Hsiung Liao

IPC: H01L27/22 ,  H01L43/12 ,  H01L43/08 ,  H01L43/02

Abstract: A semiconductor device includes a first magnetic tunneling junction (MTJ) and a second MTJ on a substrate, a first top electrode on the first MTJ and a second top electrode on the second MTJ, a passivation layer between the first MTJ and the second MTJ, and an ultra low-k (ULK) dielectric layer on and directly contacting the passivation layer and around the first MTJ and the second MTJ. Preferably, a top surface of the passivation layer includes a V-shape and a valley point of the V-shape is higher than a bottom surface of the first top electrode.

公开(公告)号：US11121312B2

公开(公告)日：2021-09-14

申请号：US16563924

申请日：2019-09-08

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Da-Jun Lin ,  Tai-Cheng Hou ,  Bin-Siang Tsai ,  Ting-An Chien

IPC: H01L43/12 ,  H01L43/02 ,  H01L27/22

Abstract: A method for fabricating semiconductor device includes the steps of: forming an inter-metal dielectric (IMD) layer on a substrate; forming a metal interconnection in the IMD layer; forming a magnetic tunneling junction (MTJ) on the metal interconnection; forming a top electrode on the MTJ; and forming a trapping layer on the top electrode for trapping hydrogen. Preferably, the trapping layer includes a concentration gradient, in which a concentration of hydrogen decreases from a top surface of the top electrode toward the MTJ.

公开(公告)号：US11119625B1

公开(公告)日：2021-09-14

申请号：US17099872

申请日：2020-11-17

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Zheng-Yang Li ,  Chung-Jung Chen ,  Chun-Man Li ,  Li-Hsin Yang ,  Ching-Pei Lin ,  Ji-Fu Kung

IPC: G06F3/0481 ,  G06F3/0484

Abstract: A remote control device for a manufacturing equipment and a method for detecting manual control are provided. The method for detecting the manual control on the manufacturing equipment includes the following steps. A cursor pattern is created. When the user interface is automatically controlled, a history location of the cursor pattern shown on a user interface of the manufacturing equipment is detected to obtain a location distribution. The location distribution is stored. A current location of the cursor pattern shown on the user interface is detected. If the current location is not within the location distribution, it is deemed that the user interface is manually controlled.